EVAL-AD5764REBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD5764REBZ
Analog Devices
'EVAL-AD5764REBZ' PDF : 32 Pages View PDF
AD5764R
VREFIN
16-BIT
DAC
OUTPUT
I/V AMPLIFIER
VOUT
LDAC
DAC
REGISTER
INPUT
REGISTER
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
Figure 37. Simplified Serial Interface of Input Loading Circuitry
for One DAC Channel
TRANSFER FUNCTION
Table 6 shows the ideal input code to output voltage
relationship for the AD5764R for both offset binary and twos
complement data coding.
Table 6. Ideal Output Voltage to Input Code Relationship for
the AD5764R
Digital Input
Analog Output
Offset Binary Data Coding
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
Twos Complement Data Coding
VOUT
+2 VREF × (32767/32768)
+2 VREF × (1/32768)
0V
−2 VREF × (1/32768)
−2 VREF × (32767/32768)
MSB
0111
0000
0000
1111
1000
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
LSB
1111
0001
0000
1111
0000
VOUT
+2 VREF × (32767/32768)
+2 VREF × (1/32768)
0V
−2 VREF × (1/32768)
−2 VREF × (32767/32768)
Preliminary Technical Data
The output voltage expression for the AD5764R is given by
VOUT
=
−2 ×VREFIN
+
4
×VREFIN
⎡
⎢⎣
D
65536
⎤
⎥⎦
where:
D is the decimal equivalent of the code loaded to the DAC.
VREFIN is the reference voltage applied at the REFAB/REFCD
pins.
ASYNCHRONOUS CLEAR (CLR)
CLR is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain CLR
low for a minimum amount of time (see Figure 3) for the
operation to complete. When the CLR signal is returned high,
the output remains at the cleared value until a new value is
programmed. If at power-on CLR is at 0 V, then all DAC
outputs are updated with the clear value. A clear can also be
initiated through software by writing the command 0x04XXXX
to the AD5764R.
Rev. PrA | Page 22 of 32
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