EVAL-AD5790SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5790SDZ' PDF : 27 Pages View PDF
Data Sheet
AD5790 FEATURES
POWER-ON TO 0 V
The AD5790 contains a power-on reset circuit that, as well as
resetting all registers to their default values, controls the output
voltage during power-up. Upon power-on, the DAC is placed in
tristate (its reference inputs are disconnected), and its output is
clamped to AGND through a ~6 kΩ resistor. The DAC remains
in this state until programmed otherwise via the control register.
This is a useful feature in applications where it is important to
know the state of the DAC output while it is in the process of
powering up.
POWER-UP SEQUENCE
To power up the part in a known safe state, ensure that VCC does
not come up while VDD is unpowered during power-on by
powering up the VDD supply before the VCC supply. If this
cannot be achieved, connect an external Schottky diode across
the VDD and VCC supplies as shown in Figure 50.
VCC VDD
VCC VDD
AD5790
Figure 50. Schottky Diode Connection
CONFIGURING THE AD5790
After power-on, the AD5790 must be configured for normal
operating mode before programming the output. To do this, the
control register must be programmed. The DAC is removed
from tristate by clearing the DACTRI bit, and the output clamp
is removed by clearing the OPGND bit. At this point, the output
goes to VREFN, unless an alternative value is first programmed to
the DAC register.
DAC OUTPUT STATE
The DAC output can be placed in one of three states, controlled
by the DACTRI and OPGND bits of the control register, as
shown in Table 15.
Table 15. Output State Truth Table
DACTRI OPGND Output State
0
0
Normal operating mode
0
1
Output is clamped via ~6 kΩ to AGND
1
0
Output is in tristate
1
1
Output is clamped via ~6 kΩ to AGND
AD5790
OUTPUT AMPLIFIER CONFIGURATION
There are a number of different ways that an output amplifier
can be connected to the AD5790, depending on the voltage
references applied and the desired output voltage span.
Unity-Gain Configuration
Figure 51 shows an output amplifier configured for unity gain.
In this configuration, the output spans from VREFN to VREFP.
VREFP
20-BIT
DAC
A1 6.8kΩ 6.8kΩ RFB
R1 RFB INV
VOUT
AD8675
ADA4898-1
ADA4004-1
VOUT
AD5790
VREFN
Figure 51. Output Amplifier in Unity-Gain Configuration
A second unity-gain configuration for the output amplifier is
one that removes an offset from the input bias currents of the
amplifier. It does this by inserting a resistance in the feedback
path of the amplifier that is equal to the output resistance of the
DAC. The DAC output resistance is 3.4 kΩ. By connecting R1
and RFB in parallel, a resistance equal to the DAC resistance is
available on chip. Because the resistors are all on one piece of
silicon, they are temperature coefficient matched. To enable this
mode of operation the RBUF bit of the control register must be
set to Logic 1. Figure 52 shows how the output amplifier is
connected to the AD5790. In this configuration, the output
amplifier is in unity gain and the output spans from VREFN to
VREFP. This unity-gain configuration allows a capacitor to be placed
in the amplifier feedback path to improve dynamic performance.
VREFP
20-BIT
DAC
RFB
R1 RFB
6.8kΩ 6.8kΩ INV
VOUT
AD5790
10pF
VOUT
AD8675
ADA4898-1
ADA4004-1
VREFN
Figure 52. Output Amplifier in Unity Gain with Amplifier Input Bias Current
Compensation
Rev. E | Page 23 of 27
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