EVAL-AD5932EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5932EBZ' PDF : 28 Pages View PDF
Data Sheet
AD5932 TO 80C51/80L51 INTERFACE
Figure 36 shows the serial interface between the AD5932 and
the 80C51/80L51 microcontroller. The microcontroller is operated
in Mode 0 so that TxD of the 80C51/80L51 drives SCLK of the
AD5932, while RxD drives the serial data line SDATA. The FSYNC
signal is again derived from a bit programmable pin on the port
(P3.3 being used in the diagram). When data is to be transmitted to
the AD5932, P3.3 is taken low. The 80C51/80L51 transmits data in
8-bit bytes; thus, only eight falling SCLK edges occur in each cycle.
To load the remaining eight bits to the AD5932, P3.3 is held low
after the first eight bits have been transmitted, and a second write
operation is initiated to transmit the second byte of data. P3.3 is
taken high following completion of the second write operation.
SCLK should idle high between the two write operations. The
80C51/80L51 outputs the serial data in an LSB-first format. The
AD5932 accepts the MSB first (the four MSBs being the control
information, the next four bits being the address, while the eight
LSBs contain the data when writing to a destination register).
Therefore, the transmit routine of the 80C51/80L51 must
consider this and rearrange the bits so that the MSB is output first.
80C51/80L511
AD59321
P3.3
RxD
TxD
FSYNC
SDATA
SCLK
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 36. 80C51/80L51 to AD5932 Interface
AD5932
AD5932 TO DSP56002 INTERFACE
Figure 37 shows the interface between the AD5932 and the
DSP56002. The DSP56002 is configured for normal mode,
asynchronous operation with a gated internal clock (SYN = 0,
GCK = 1, SCKD = 1). The frame sync pin is generated internally
(SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0),
and the frame sync signal frames the 16 bits (FSL = 0). The
frame sync signal is available on Pin SC2, but it must be inverted
before being applied to the AD5932. The interface to the
DSP56000/DSP56001 is similar to that of the DSP56002.
DSP560021
AD59321
SC2
STD
SCK
FSYNC
SDATA
SCLK
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 37. DSP56002 to AD5932 Interface
Rev. C | Page 21 of 28
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