EVAL-AD7152EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7152EBZ' PDF : 24 Pages View PDF
AD7152/AD7153
The user can also access any unique register (address) on a
one-to-one basis without having to update all the registers.
However, the address pointer register contents cannot be read.
If an incorrect address pointer location is accessed, or if the user
allows the autoincrementer to exceed the required register
address, apply the following requirements:
In read mode, the AD7152/AD7153 continue to output
various internal register contents until the master device
issues a no acknowledge, start, or stop condition. The
contents of the address pointers autoincrementer are reset
to point to the status register at Address 0x00 when a stop
condition is received at the end of a read operation. This
allows the status register to be read (polled) continually
without having to constantly write to the address pointer.
In write mode, the data for the invalid address is not
loaded into the registers of the AD7152/AD7153, but
an acknowledge is issued by the AD7152/AD7153.
Data Sheet
AD7152/AD7153 RESET
To reset the AD7152/AD7153 without having to reset the entire
I2C bus, an explicit reset command is provided. This command
uses a particular address pointer word as a command word to
reset the device and upload all default settings. The AD7152/
AD7153 do not respond to the I2C bus commands (no acknowl-
edge) during the default values upload for approximately 150 μs
(maximum 200 μs).
The reset command address word is 0xBF.
GENERAL CALL
When a master issues a slave address consisting of seven 0s with
the eighth bit (R/W bit) set to 0, this is called the general call
address. The general call address is for addressing every device
connected to the I2C bus. The AD7152/AD7153 acknowledge
this address and read the following data byte.
If the second byte is 0x06, the AD7152/AD7153 are reset,
completely uploading all default values. The AD7152/AD7153
do not respond to the I2C bus commands (no acknowledge)
during the default values upload for approximately 150 μs
(maximum 200 μs).
The AD7152/AD7153 do not acknowledge any other general call
commands.
SDA
SCL S
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
START ADDR R/W ACK SUBADDRESS
ACK
DATA
ACK
Figure 22. Bus Data Transfer
P
STOP
WRITE
SEQUENCE
S SLAVE ADDR A(S) SUB ADDR
LSB = 0
A(S)
DATA
A(S)
LSB = 1
READ
SEQUENCE
S SLAVE ADDR A(S)
SUB ADDR A(S) S SLAVE ADDR A(S)
DATA
DATA
A(M)
A(S) P
DATA
A(M) P
Table 5. I2C Abbreviation
Abbreviation
S
P
A(S)
A(M)
A(S)
A(M)
ACK
R/W
Figure 23. Write and Read Sequences
Definition
Start bit
Stop bit
Acknowledge by slave
Acknowledge by master
No acknowledge by slave
No acknowledge by master
Acknowledge
Read/write
Rev. A | Page 12 of 24
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