EVAL-AD7265EDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD7265EDZ
Analog Devices
'EVAL-AD7265EDZ' PDF : 27 Pages View PDF
ANALOG INPUT SELECTION
The analog inputs of the AD7265 can be configured as single-
ended or true differential via the SGL/DIFF logic pin, as shown
in Figure 31. If this pin is tied to a logic low, the analog input
channels to each on-chip ADC are set up as three true differen-
tial pairs. If this pin is at logic high, the analog input channels to
each on-chip ADC are set up as six single-ended analog inputs.
The required logic level on this pin needs to be established prior
to the acquisition time and remain unchanged during the con-
version time until the track-and-hold has returned to track. The
track-and-hold returns to track on the 13th rising edge of SCLK
after the CS falling edge (see Figure 41). If the level on this pin
is changed, it is recognized by the AD7265; therefore, it is
necessary to keep the same logic level during acquisition and
conversion to avoid corrupting the conversion in progress.
For example, in Figure 31, the SGL/DIFF pin is set at logic high
for the duration of both the acquisition and conversion times
so the analog inputs are configured as single ended for that
conversion (Sampling Point A). The logic level of the SGL/DIFF
changed to low after the track-and-hold returned to track and
prior to the required acquisition time for the next sampling
instant at Point B; therefore, the analog inputs are configured as
differential for that conversion.
A
B
CS
tACQ
SCLK
1
14
1
14
SGL/DIFF
Figure 31. Selecting Differential or Single-Ended Configuration
AD7265
The channels used for simultaneous conversions are selected via
the multiplexer address input pins, A0 to A2. The logic states of
these pins also need to be established prior to the acquisition
time; however, they may change during the conversion time,
provided that the mode is not changed. If the mode is changed
from fully differential to pseudo-differential, for example, then
the acquisition time would start again from this point. The
selected input channels are decoded as shown in Table 6.
The analog input range of the AD7265 can be selected as 0 V to
VREF or 0 V to 2 × VREF via the RANGE pin. This selection is
made in a similar fashion to that of the SGL/DIFF pin by setting
the logic state of the RANGE pin a time tacq prior to the falling
edge of CS. Subsequent to this, the logic level on this pin can be
altered after the third falling edge of SCLK. If this pin is tied to a
logic low, the analog input range selected is 0 V to VREF. If this
pin is tied to a logic high, the analog input range selected is 0 V
to 2 × VREF.
OUTPUT CODING
The AD7265 output coding is set to either twos complement or
straight binary, depending on which analog input configuration
is selected for a conversion. Table 5 shows which output coding
scheme is used for each possible analog input configuration.
Table 5. AD7265 Output Coding
SGL/DIFF
Range
DIFF
0 V to VREF
DIFF
0 V to 2 × VREF
SGL
0 V to VREF
SGL
0 V to 2 × VREF
PSEUDO DIFF
0 V to VREF
PSEUDO DIFF
0 V to 2 × VREF
Output Coding
Twos complement
Twos complement
Straight binary
Twos complement
Straight binary
Twos complement
Table 6. Analog Input Type and Channel Selection
SGL/DIFF
1
1
1
1
1
1
0
0
0
0
0
0
A2
A1
A0
VIN+
0
0
0
V A1
0
0
1
V A2
0
1
0
VA3
0
1
1
VA4
1
0
0
V A5
1
0
1
V A6
0
0
0
V A1
0
0
1
V A1
0
1
0
V A3
0
1
1
V A3
1
0
0
V A5
1
0
1
VA5
ADC A
VIN−
AGND
AGND
AGND
AGND
AGND
AGND
VA2
VA2
VA4
VA4
VA6
VA6
ADC B
VIN+
VIN−
VB1
AGND
VB2
AGND
VB3
AGND
VB4
AGND
VB5
AGND
VB6
AGND
VB1
VB2
VB1
VB2
VB3
VB4
VB3
VB4
VB5
VB6
VB5
VB6
Comment
Single ended
Single ended
Single ended
Single ended
Single ended
Single ended
Fully differential
Pseudo differential
Fully differential
Pseudo differential
Fully differential
Pseudo differential
Rev. A | Page 17 of 28
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