EVAL-AD7265EDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD7265EDZ
Analog Devices
'EVAL-AD7265EDZ' PDF : 27 Pages View PDF
CS
SCLK
THE PART BEGINS
TO POWER UP.
tPOWER-UP2
1
10
14
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
AD7265
1
14
DOUTA
DOUTB
INVALID DATA
VALID DATA
Figure 38. Exiting Full Power-Down Mode
POWER-UP TIMES
As described in detail, the AD7265 has two power-down
modes, partial power-down and full power-down. This section
deals with the power-up time required when coming out of
either of these modes. It should be noted that the power-up
times, as explained in this section, apply with the recommended
capacitors in place on the DCAPA and DCAPB pins.
To power up from full power-down (whether using an internal
or external reference), approximately 1.5 ms should be allowed
from the falling edge of CS, shown as tPOWER-UP2 in Figure 38.
Powering up from partial power-down requires much less time.
The power-up time from partial power-down is typically 1 μs;
however, if using the internal reference, then the AD7265 must
be in partial power-down for at least 67 μs in order for this
power-up time to apply.
can be used to make significant power savings. However, the
AD7265 quiescent current is low enough that even without
using the power-down options, there is a noticeable variation in
power consumption with sampling rate. This is true whether a
fixed SCLK value is used or if it is scaled with the sampling rate.
Figure 39 and Figure 40 show plots of power vs. the throughput
rate when operating in normal mode for a fixed maximum
SCLK frequency, and an SCLK frequency that scales with the
sampling rate with VDD = 3 V and VDD = 5 V, respectively. In all
cases, the internal reference was used.
10.0
TA = 25°C
9.5
9.0
8.5
8.0
When power supplies are first applied to the AD7265, the ADC
may power up in either of the power-down modes or normal
mode. Because of this, it is best to allow a dummy cycle to
elapse to ensure the part is fully powered up before attempting a
valid conversion. Likewise, if it is intended to keep the part in
the partial power-down mode immediately after the supplies are
applied, then two dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10th SCLK falling
edge (see Figure 34); in the second cycle, CS must be brought
high before the 10th SCLK edge but after the second SCLK
falling edge (see Figure 35). Alternatively, if it is intended to
place the part in full power-down mode when the supplies are
applied, then three dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10th SCLK falling
edge (see Figure 34); the second and third dummy cycles place
the part in full power-down (see Figure 37).
Once supplies are applied to the AD7265, enough time must be
allowed for any external reference to power up and charge the
various reference buffer decoupling capacitors to their final values.
7.5
7.0
VARIABLE SCLK
16MHz SCLK
6.5
6.0
5.5
5.0
0
100 200 300 400 500 600 700 800 900 1000
THROUGHPUT (kSPS)
Figure 39. Power vs. Throughput in Normal Mode with VDD = 3 V
25
TA = 25°C
23
21
19
VARIABLE SCLK
17
15
16MHz SCLK
13
11
9
POWER vs. THROUGHPUT RATE
The power consumption of the AD7265 varies with throughput
rate. When using very slow throughput rates and as fast an
SCLK frequency as possible, the various power-down options
7
5
0 100 200 300 400 500 600 700 800 900 1000
THROUGHPUT (kSPS)
Figure 40. Power vs. Throughput in Normal Mode with VDD = 5 V
Rev. A | Page 21 of 28
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