EVAL-AD73311LEB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD73311LEB' PDF : 36 Pages View PDF
AD73311L
Table XI. Control Register A Description
CONTROL REGISTER A
7
6
RESET DC2
5
DC1
4
DC0
3
SLB
2
DLB
1
0
MM DATA/PGM
Bit Name
Description
0 DATA/PGM Operating Mode (0 = Program; 1 = Data Mode)
1 MM
Mixed Mode (0 = Off; 1 = Enabled)
2 DLB
Digital Loop-Back Mode (0 = Off; 1 = Enabled)
3 SLB
SPORT Loop-Back Mode (0 = Off; 1 = Enabled)
4 DC0
Device Count (Bit 0)
5 DC1
Device Count (Bit 1)
6 DC2
7 RESET
Device Count (Bit 2)
Software Reset (0 = Off; 1 = Initiates Reset)
CONTROL REGISTER B
7
CEE
Table XII. Control Register B Description
6
5
4
MCD2 MCD1 MCD0
3
SCD1
2
SCD0
1
DIR1
0
DIR0
Bit Name
0 DIR0
1 DIR1
2 SCD0
3 SCD1
4 MCD0
5 MCD1
6 MCD2
7 CEE
Description
Decimation/Interpolation Rate (Bit 0)
Decimation/Interpolation Rate (Bit 1)
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
Control Echo Enable (0 = Off; 1 = Enabled)
CONTROL REGISTER C
7
–
Table XIII. Control Register C Description
6
5
4
3
2
RU PUREF PUDAC PUADC –
1
0
–
PU
Bit Name
0 PU
1 Reserved
2 Reserved
3 PUADC
4 PUDAC
5 PUREF
6 RU
7 Reserved
Description
Power-Up Device (0 = Power Down; 1 = Power On)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
ADC Power (0 = Power Down; 1 = Power On)
DAC Power (0 = Power Down; 1 = Power On)
REF Power (0 = Power Down; 1 = Power On)
REFOUT Use (0 = Disable REFOUT; 1 = Enable
REFOUT)
Must Be Programmed to Zero (0)
–14–
REV. A
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