EVAL-AD73311LEB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD73311LEB' PDF : 36 Pages View PDF
AD73311L
APPENDIX D
Configuring a cascade of two AD73311Ls to Operate in Mixed
Mode
This section describes a typical sequence of control words that
would be sent to a cascade of two AD73311Ls to configure
them for operation in mixed mode. It is not intended to be a
definitive initialization sequence, but will show users the typical
input/output events that occur in the programming and opera-
tion phases.1 This description panel refers to Table XXII.
Steps 1–5 detail the transfer of the control words to Control
Register A, which programs the devices for Mixed-Mode opera-
tion. In Step 1, we have the first output sample event following
device reset. The SDOFS signal is simultaneously raised on both
devices, which prepares the DSP Rx register to accept the ADC
word from Device 2 while SDOFS from Device 1 becomes an
SDIFS to Device 2. The cascade is configured as nonFSLB,
which means that the DSP has control over what is transmitted
to the cascade2 and in this case we will not transmit to the
devices until both output words have been received from the
AD73311Ls.
In Step 2, we observe the status of the devices following the
reception of the Device 2 output word. The DSP has received
the ADC word from Device 2, while Device 2 has received the
output word from Device 1. At this stage, the SDOFS of Device
2 is again raised because Device 2 has received Channel 1’s
output word and, as it is not addressed to Device 2, it is passed
on to the DSP.
In Step 3 the DSP has now received both ADC words. Typi-
cally, an interrupt will be generated following reception of the
two output words by the DSP (this involves programming the
DSP to use autobuffered transfers of two words). The transmit
register of the DSP is loaded with the control word destined for
Device 2. This generates a transmit frame-sync (TFS) that is
input to the SDIFS input of the AD73311L (Device 1) to indi-
cate the start of transmission.
In Step 4, Device 1 now contains the Control Word destined for
Device 2. The address field is decremented, SDOFS1 is raised
(internally) and the Control word is passed on to Channel 2.
The Tx register of the DSP has now been updated with the
Control Word destined for Device 1 (this can be done using
autobuffering of transmit or by handling transmit interrupts
following each word sent).
In Step 5 each device has received a control word that addresses
Control Register A and sets the device count field equal to two
devices and programs the devices into Mixed Mode—MM and
PGM/DATA set to one. Following Step 5, the device has been
programmed into mixed-mode although none of the analog
sections have been powered up (controlled by Control Register
C). Steps 6–10 detail update of Control Register B in mixed-
mode. In Steps 6–8 the ADC samples, which are invalid as the
ADC section is not yet powered up, are transferred to the DSP’s
Rx section. In the subsequent interrupt service routine the Tx
Register is loaded with the control word for Device 2. In Steps
9–10, Devices 1 and 2 are loaded with a control word setting for
Control Register B which programs DMCLK = MCLK, the
sampling rate to DMCLK/256, SCLK = DMCLK/2.
Steps 11–17 are similar to Steps 6–12 except that Control Reg-
ister C is programmed to power up all analog sections (ADC,
DAC, Reference = 2.4 V, REFOUT). In Steps 16–17, DAC
words are sent to the device—both DAC words are necessary
as each device will only update its DAC when the device has
counted a number of SDIFS pulses, accompanied by DAC words
(in mixed-mode, the MSB = 0), that is equal to the device count
field of Control Register A3. As the devices are in mixed mode,
the serial port interrogates the MSB of the 16-bit word sent to
determine whether it contains DAC data or control information.
DAC words should be sent in the sequence Channel 2 followed
by Device 1.
Steps 11–17 illustrate the implementation of Control Register
update and DAC update in a single sample period. Note that
this combination is not possible in the FSLB configuration.2
Steps 18–25 illustrate a Control Register readback cycle. In Step
22, both devices have received a Control Word that addresses
Control Register C for readback (Bit 14 of the Control Word =
1). When the devices receive the readback request, the register
contents are loaded to the serial registers as shown in Step 23.
SDOFS is raised in both devices, which causes these readback
words to be shifted out toward the DSP. In Step 24, the DSP
has received the Device 2 readback word while Device 2 has
received the Device 1 readback word (note that the address field
in both words has been decremented to 111b). In Step 25, the
DSP has received the Device 1 readback word (its address field
has been further decremented to 110b).
Steps 26–30 detail an ADC and DAC update cycle using the
nonFSLB configuration. In this case no Control Register update
is required.
NOTES
1This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are
enabled. It is important to ensure there is no latency (separation) between
control words in a cascade configuration. This is especially the case when
programming Control Registers A and B.
2Mixed mode operation with the FSLB configuration is more restricted in that
the number of words sent to the cascade equals the number of devices in the
cascade, which means that DAC updates may need to be substituted with a
register write or read.
3In mixed mode, DAC update is done using the same SDIFS counting scheme
as in normal data mode with the exception that only DAC words (MSB set to
zero) are recognized as being able to increment the frame sync counters.
–34–
REV. A
Share Link: 
