EVAL-AD7606SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD7606SDZ
Analog Devices
'EVAL-AD7606SDZ' PDF : 36 Pages View PDF
Analog Input Antialiasing Filter
An analog antialiasing filter (a second-order Butterworth) is also
provided on the AD7606/AD7606-6/AD7606-4. Figure 37 and
Figure 38 show the frequency and phase response, respectively,
of the analog antialiasing filter. In the ±5 V range, the −3 dB
frequency is typically 15 kHz. In the ±10 V range, the −3 dB
frequency is typically 23 kHz.
5
0
–5
AVCC, VDRIVE = 5V
FSAMPLE = 200kSPS
TA = 25°C
–10
±10V RANGE
±5V RANGE
–15
–20 ±10V RANGE
–40
–25
+25
+85
–30 ±5V RANGE
–40
–35
+25
+85
–40
100
0.1dB
10,303
9619
9326
3dB
24,365Hz
23,389Hz
22,607Hz
0.1dB
5225
5225
4932
3dB
16,162Hz
15,478Hz
14,990Hz
1k
10k
INPUT FREQUENCY (Hz)
100k
Figure 37. Analog Antialiasing Filter Frequency Response
18
16
±5V RANGE
14
12
10 ±10V RANGE
8
6
4
2
0
–2
–4 AVCC, VDRIVE = 5V
–6
FSAMPLE = 200kSPS
TA = 25°C
–8
10
1k
10k
INPUT FREQUENCY (Hz)
Figure 38. Analog Antialias Filter Phase Response
100k
Track-and-Hold Amplifiers
The track-and-hold amplifiers on the AD7606/AD7606-6/
AD7606-4 allow the ADC to accurately acquire an input sine wave
of full-scale amplitude to 16-bit resolution. The track-and-hold
amplifiers sample their respective inputs simultaneously on the
rising edge of CONVST x. The aperture time for the track-and-
AD7606/AD7606-6/AD7606-4
hold (that is, the delay time between the external CONVST x
signal and the track-and-hold actually going into hold) is well
matched, by design, across all eight track-and-holds on one
device and from device to device. This matching allows more
than one AD7606/AD7606-6/AD7606-4 device to be sampled
simultaneously in a system.
The end of the conversion process across all eight channels is
indicated by the falling edge of BUSY; and it is at this point that the
track-and-holds return to track mode, and the acquisition time
for the next set of conversions begins.
The conversion clock for the part is internally generated, and
the conversion time for all channels is 4 μs on the AD7606,
3 μs on the AD7606-6, and 2 μs on the AD7606-4. On the AD7606,
the BUSY signal returns low after all eight conversions to indicate
the end of the conversion process. On the falling edge of BUSY,
the track-and-hold amplifiers return to track mode. New data
can be read from the output register via the parallel, parallel
byte, or serial interface after BUSY goes low; or, alternatively,
data from the previous conversion can be read while BUSY is
high. Reading data from the AD7606/AD7606-6/AD7606-4
while a conversion is in progress has little affect on performance
and allows a faster throughput to be achieved. In parallel mode
at VDRIVE > 3.3 V, the SNR is reduced by ~1.5 dB when reading
during a conversion.
ADC TRANSFER FUNCTION
The output coding of the AD7606/AD7606-6/AD7606-4 is
twos complement. The designed code transitions occur midway
between successive integer LSB values, that is, 1/2 LSB and 3/2 LSB.
The LSB size is FSR/65,536 for the AD7606. The ideal transfer
characteristic for the AD7606/AD7606-6/AD7606-4 is shown
in Figure 39.
011...111
011...110
VIN
REF
±10V CODE = 10V × 32,768 × 2.5V
VIN
REF
±5V CODE = 5V × 32,768 × 2.5V
000...001
000...000
111...111
+FS – (–FS)
LSB =
216
100...010
100...001
100...000
–FS + 1/2LSB 0V – 1/2LSB +FS – 3/2LSB
ANALOG INPUT
+FS
±10V RANGE +10V
±5V RANGE +5V
MIDSCALE –FS
0V
–10V
0V
–5V
LSB
305µV
152µV
Figure 39. AD7606/AD7606-6/AD7606-4 Transfer Characteristics
The LSB size is dependent on the analog input range selected.
Rev. 0 | Page 23 of 36
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