EVAL-AD7606SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD7606SDZ
Analog Devices
'EVAL-AD7606SDZ' PDF : 36 Pages View PDF
AD7606/AD7606-6/AD7606-4
Parameter
t13
t144
t15
t16
t17
SERIAL READ OPERATION
fSCLK
t18
t19 4
t20
t21
t22
t23
FRSTDATA OPERATION
t24
t25
t26
Limit at TMIN, TMAX
Min Typ Max
16
20
25
30
16
21
25
32
6
6
22
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Delay from CS until DB[15:0] three-state disabled
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
Data access time after RD falling edge
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
Data hold time after RD falling edge
CS to DB[15:0] hold time
Delay from CS rising edge to DB[15:0] three-state enabled
0.4 tSCLK
0.4 tSCLK
7
Frequency of serial read clock
23.5 MHz VDRIVE above 4.75 V
17
MHz VDRIVE above 3.3 V
14.5 MHz VDRIVE above 2.7 V
11.5 MHz VDRIVE above 2.3 V
Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS
until MSB valid
15
ns
VDRIVE above 4.75 V
20
ns
VDRIVE above 3.3 V
30
ns
VDRIVE = 2.3 V to 2.7 V
Data access time after SCLK rising edge
17
ns
VDRIVE above 4.75 V
23
ns
VDRIVE above 3.3 V
27
ns
VDRIVE above 2.7 V
34
ns
VDRIVE above 2.3 V
ns SCLK low pulse width
ns SCLK high pulse width
SCLK rising edge to DOUTA/DOUTB valid hold time
22
ns CS rising edge to DOUTA/DOUTB three-state enabled
Delay from CS falling edge until FRSTDATA three-state disabled
15
ns
VDRIVE above 4.75 V
20
ns
VDRIVE above 3.3 V
25
ns
VDRIVE above 2.7 V
30
ns
VDRIVE above 2.3 V
ns Delay from CS falling edge until FRSTDATA high, serial mode
15
ns
VDRIVE above 4.75 V
20
ns
VDRIVE above 3.3 V
25
ns
VDRIVE above 2.7 V
30
ns
VDRIVE above 2.3 V
Delay from RD falling edge to FRSTDATA high
16
ns
VDRIVE above 4.75 V
20
ns
VDRIVE above 3.3 V
25
ns
VDRIVE above 2.7 V
30
ns
VDRIVE above 2.3 V
Rev. 0 | Page 8 of 36
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