EVAL-AD7621CB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7621CB' PDF : 32 Pages View PDF
INTERFACES
DIGITAL INTERFACE
The AD7621 has a versatile digital interface that can be set up
as either a serial or parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The
AD7621 digital interface also accommodates 2.5 V, 3.3 V, or 5
V logic with either OVDD at 2.5 V or 3.3 V. OVDD defines the
logic high output voltage. In most applications, the OVDD
supply pin of the AD7621 is connected to the host system
interface 2.5 V or 3.3 V digital supply. Finally, by using the
OB/2C input pin, both twos complement or straight binary
coding can be used.
The two signals, CS and RD, control the interface. When at
least one of these signals is high, the interface outputs are in
high impedance. Usually, CS allows the selection of each
AD7621 in multicircuit applications and is held low in a single
AD7621 design. RD is generally used to enable the conversion
result on the data bus.
RESET
The RESET input is used to reset the AD7621 and generate a
fast initialization. A rising edge on RESET aborts the current
conversion (if any) and tristates the data bus. The falling edge
of RESET clears the data bus and engages the initialization
process indicated by pulsing BUSY high. Conversions can take
place after the falling edge of BUSY. Refer to Figure 33 for the
RESET timing details.
t9
RESET
CNVST
DATA
BUSY
t38
t39
t8
Figure 33. RESET Timing
AD7621
PARALLEL INTERFACE
The AD7621 is configured to use the parallel interface when
SER/PAR is held low.
Master Parallel Interface
Data can be continuously read by tying CS and RD low thus
requiring minimal microprocessor connections. However, in
this mode the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 34 details the timing for this mode.
CS = RD = 0
t1
CNVST
BUSY
DATA
BUS
t10
t4
t3
PREVIOUS CONVERSION DATA
t11
NEW DATA
Figure 34. Master Parallel Data Timing for Reading (Continuous Read)
Slave Parallel Interface
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 35 and
Figure 36, respectively. When the data is read during the
conversion, it is recommended that it is read-only during the
first half of the conversion phase. This avoids any potential
feedthrough between voltage transients on the digital interface
and the most critical analog conversion circuitry.
CS
RD
BUSY
DATA
BUS
CURRENT
CONVERSION
t12
t13
Figure 35. Slave Parallel Data Timing for Reading (Read After Convert)
Rev. A | Page 21 of 32
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