EVAL-AD7621CB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7621CB' PDF : 32 Pages View PDF
AD7621
Pin No.
13
14
15
16
17
18
19
20
21
22
23
24
Mnemonic
D4
or EXT/INT
Type1
DI/O
Description
When SER/PAR = low, this output is used as Bit 4 of the parallel port data output bus.
When SER/PAR = high, serial clock source select. This input is used to select the internally generated
(master ) or external (slave) serial data clock.
When EXT/INT = low: master mode. The internal serial clock is selected on SCLK output.
When EXT/INT = high: slave mode. The output data is synchronized to an external clock signal, gated
by CS, connected to the SCLK input.
D5
DI/O
or INVSYNC
D6
DI/O
or INVSCLK
D7
DI/O
or RDC
or SDIN
OGND
P
OVDD
P
DVDD
P
DGND
P
D8
DO
or SDOUT
D9
DI/O
or SCLK
D10
DO
or SYNC
D11
DO
or RDERROR
When SER/PAR = low this output is used as Bit 5 of the parallel port data output bus.
When SER/PAR = high, invert sync select. In serial master mode (EXT/INT = low), this input is used to
select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
When SER/PAR = low this output is used as Bit 6 of the parallel port data output bus.
Invert SCLK Select. In all serial modes, this input is used to invert the SCLK signal.
Bit 7 of the Parallel Port Data Output Bus.
When SER/PAR = high, read during convert. When using Serial Master mode (EXT/INT = low), RDC is
used to select the read mode.
When RDC = high, the previous conversion result is read during current conversion and the period of
SCLK changes (see the Master Serial Interface section).
When RDC = low (read after convert), the current result is read after conversion.
Serial Data In. When using serial slave mode, (EXT/INT = high), SDIN could be used as a data input to
daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data
level on SDIN is output on SDOUT with a delay of 16 SCLK periods after the initiation of the read
sequence.
Input/Output Interface Digital Power Ground.
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface
(2.5 V or 3 V).
Digital Power. Nominally at 2.5 V.
Digital Power Ground.
When SER/PAR = low this output is used as Bit 8 of the parallel port data output bus.
When SER/PAR = high, serial data output. In serial mode, this pin is used as the serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7621 provides the
conversion result, MSB first, from its internal shift register. The data format is determined by the logic
level of OB/2C.
In master mode (EXT/INT = low). SDOUT is valid on both edges of SCLK.
In slave mode (EXT/INT = high):
When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
Parallel Port Data Output Bus Bit 9. When SER/PAR = low, this output is used as Bit 9 of the parallel port
data output bus.
Serial Clock. When SER/PAR = high, serial clock. In all serial modes, this pin is used as the serial data
clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
When SER/PAR = low, this output is used as Bit 10 of the parallel port data output bus.
When SER/PAR = high, frame synchronization. In serial master mode (EXT/INT= low), this output is
used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while
SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while
SDOUT output is valid.
Parallel Port Data Output Bus Bit 11. When SER/PAR = low, this output is used as Bit 11 of the parallel
port data output bus.
Read Error. When SER/PAR = high, read error. In serial slave mode (EXT/INT = high), this output is used
as an incomplete read error flag. If a data read is started and not completed when the current
conversion is complete, the current data is lost and RDERROR is pulsed high.
Rev. A | Page 9 of 32
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