EVAL-AD7625FMCZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7625FMCZ' PDF : 24 Pages View PDF
Data Sheet
AD7625
TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Time Between Conversions1
Acquisition Time
CNV± High Time
CNV± to D± (MSB) Delay
CNV± to Last CLK± (LSB) Delay
CLK± Period2
CLK± Frequency
CLK± to DCO± Delay (Echoed-Clock Mode)
DCO± to D± Delay (Echoed-Clock Mode)
CLK± to D± Delay
Symbol
tCYC
tACQ
tCNVH
tMSB
tCLKL
tCLK
fCLK
tDCO
tD
tCLKD
Min
Typ
166
40
10
(tCYC − tMSB + tCLKL)/n 4
250
0
4
0
0
4
Max
Unit
10,000
ns
ns
40
ns
145
ns
110
ns
3.33
ns
300
MHz
7
ns
1
ns
7
ns
1 The maximum time between conversions is 10,000 ns. If CNV± is left idle for a time greater than the maximum value of tCYC, the subsequent conversion result is invalid.
2 For the minimum CLK period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) that are read. In echoed-clock interface
mode, n = 16; in self-clocked interface mode, n = 18.
Rev. B | Page 5 of 24
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