EVAL-AD7667CB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7667CB' PDF : 28 Pages View PDF
AD7667
Table 4. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
BUSY HIGH Width Maximum
Symbol
t18
t19
t19
t20
t21
t22
t23
t24
t24
0
0
1
1
0
1
0
1
Unit
3
17
17
17
ns
25
50
100
200
ns
40
70
140
280
ns
12
22
50
100
ns
7
21
49
99
ns
4
18
18
18
ns
2
4
30
80
ns
3
55
130
290
ns
1.5
2
3
5.25
µs
Rev. 0 | Page 6 of 28
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