EVAL-AD7687SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7687SDZ' PDF : 28 Pages View PDF
Data Sheet
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7687 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 41 and the
corresponding timing is given in Figure 42.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the BUSY signal indicator. When
the conversion is complete, SDO goes from high impedance to
low. With a pull-up on the SDO line, this transition can be used
AD7687
as an interrupt signal to initiate the data readback controlled by
the digital host. The AD7687 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge, or SDI going high, whichever is earlier,
the SDO returns to high impedance.
CNV
SDI AD7687 SDO
CS1
CONVERT
VIO
DIGITAL HOST
47kΩ
DATA IN
SCK
IRQ
CLK
Figure 41. CS Mode 4-Wire with BUSY Indicator Connection Diagram
CNV
ACQUISITION
tCONV
CONVERSION
tCYC
tACQ
ACQUISITION
tSSDICNV
SDI
tHSDICNV
SCK
SDO
tSCKL
tSCK
1
2
3
15
16
17
tHSDO
tSCKH
tDSDO
tEN
D15
D14
tDIS
D1
D0
Figure 42. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing
Rev. B | Page 21 of 28
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