EVAL-AD7687SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7687SDZ' PDF : 26 Pages View PDF
AD7687
CS MODE 4-WIRE, NO BUSY INDICATOR
This mode is usually used when multiple AD7687s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7687s is shown in
Figure 39 and the corresponding timing is given in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
Data Sheet
time and held high until the maximum conversion time to
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7687 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing low its SDI input, which consequently outputs the
MSB onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the 16th SCK
falling edge, or when SDI goes high, whichever is earlier, SDO
returns to high impedance and another AD7687 can be read.
CS2
CS1
CONVERT
CNV
SDI AD7687 SDO
CNV
SDI AD7687 SDO
DIGITAL HOST
SCK
SCK
DATA IN
CLK
Figure 39. CS Mode 4-Wire, No BUSY Indicator Connection Diagram
CNV
ACQUISITION
tCONV
CONVERSION
tSSDICNV
SDI(CS1)
tHSDICNV
tCYC
tACQ
ACQUISITION
SDI(CS2)
SCK
SDO
tSCKL
tSCK
1
2
3
14
15
16
tHSDO
tSCKH
tEN
tDSDO
D15 D14 D13
D1 D0
17
18
D15 D14
30
31
32
tDIS
D1 D0
Figure 40. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing
Rev. B | Page 20 of 28
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