EVAL-AD7691SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7691SDZ' PDF : 28 Pages View PDF
Data Sheet
AD7691
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is normally used when a single AD7691 is connected
to an SPI-compatible digital host with an interrupt input, and it
is desired to keep CNV, which is used to sample the analog
input, independent of the signal used to select the data reading.
This requirement is particularly important in applications
where low jitter on CNV is desired.
The connection diagram is shown in Figure 41, and the
corresponding timing is given in Figure 42.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition is used as an interrupt signal to initiate the
data readback controlled by the digital host. When using this
option, select the value of the pull-up resistor such that it
CNV
ACQUISITION
tCONV
CONVERSION
maintains an appropriate rise time on the SDO line for the
application. This is a function of the resistance of the pull-up
and the capacitance of the SDO line. The AD7691 then enters
the acquisition phase and powers down. The data bits are
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge is
used to capture the data, a digital host using the SCK falling
edge can allow a faster reading rate, provided it has an
acceptable hold time. After the optional 19th SCK falling edge,
or SDI going high, whichever occurs first, SDO returns to high
impedance.
CNV
SDI AD7691 SDO
SCK
CS1
CONVERT
VIO
DIGITAL HOST
47kΩ
DATA IN
IRQ
CLK
Figure 41. 4-Wire CS Mode with Busy Indicator Connection Diagram
tCYC
tACQ
ACQUISITION
tSSDICNV
SDI
tHSDICNV
SCK
SDO
tSCKL
tSCK
1
2
3
17
18
19
tHSDO
tSCKH
tDSDO
tEN
D17
D16
tDIS
D1
D0
Figure 42. 4-Wire CS Mode with Busy Indicator Serial Interface Timing
Rev. E | Page 21 of 28
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