EVAL-AD7712EB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7712EB' PDF : 28 Pages View PDF
AD7712
TIMING CHARACTERISTICS1, 2
(DVDD = +5 V ؎ 5%; AVDD = +5 V or +10 V3 ؎ 5%; VSS = 0 V or –5 V ؎ 5%; AGND = DGND =
0 V; fCLKIN =10 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
(A, S Versions)
Unit
Conditions/Comments
fCLK
4,
IN
5
tCLK IN LO
tCLK IN HI
tr6
tf6
t1
Self-Clocking Mode
t2
t3
t4
t5
t6
t77
t87
t9
t10
t14
t15
t16
t17
t18
t19
400
10
8
0.4 ϫ tCLK IN
0.4 ϫ tCLK IN
50
50
1000
0
0
2 ϫ tCLK IN
0
4 ϫ tCLK IN + 20
4 ϫ tCLK IN + 20
tCLK IN/2
tCLK IN/2 + 30
tCLK IN/2
3 ϫ tCLK IN/2
50
0
4 ϫ tCLK IN + 20
4 ϫ tCLK IN
0
10
kHz min
MHz max
MHz
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns nom
ns nom
ns min
ns min
ns max
ns min
ns min
ns min
Master Clock Frequency: Crystal Oscillator or
Externally Supplied
AVDD = 5 V ± 5%
For Specified Performance
AVDD = 5.25 V to 10.5 V
Master Clock Input Low Time; tCLK IN = 1/fCLK IN
Master Clock Input High Time
Digital Output Rise Time; Typically 20 ns
Digital Output Fall Time; Typically 20 ns
SYNC Pulse Width
DRDY to RFS Setup Time; tCLK IN = 1/fCLK IN
DRDY to RFS Hold Time
A0 to RFS Setup Time
A0 to RFS Hold Time
RFS Low to SCLK Falling Edge
Data Access Time (RFS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
A0 to TFS Setup Time
A0 to TFS Hold Time
TFS to SCLK Falling Edge Delay Time
TFS to SCLK Falling Edge Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
NOTES
1Guaranteed by design, not production tested. Sample tested during initial release and after any redesign or process change that may affect this parameter. All input
signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 11 to 14.
3The AD7712 is specified with a 10 MHz clock for AVDD voltages of 5 V ± 5%. It is specified with an 8 MHz clock for AVDD voltages greater than 5.25 V and less
than 10.5 V.
4CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7712 is not in STANDBY mode. If no clock is present in this case, the
device can draw higher current than specified and possibly become uncalibrated.
5The AD7712 is production tested with fCLK IN at 10 MHz (8 MHz for AVDD < 5.25 V). It is guaranteed by characterization to operate at 400 kHz.
6Specified using 10% and 90% points on waveform of interest.
7These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
REV. F
–5–
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