AD7764
Parameter
REFERENCE INPUT/OUTPUT
VREF Input Voltage
VREF Input DC Leakage Current
VREF Input Capacitance
DIGITAL INPUT/OUTPUT
MCLK Input Amplitude
Input Capacitance
Input Leakage Current
VINH
VINL
VOH 4
VOL
ON-CHIP DIFFERENTIAL AMPLIFIER
Input Impedance
Bandwidth for 0.1 dB Flatness
Common-Mode Input Voltage
Common-Mode Output Voltage
POWER REQUIREMENTS
AVDD1 (Modulator Supply)
AVDD2 (General Supply)
AVDD3 (Differential Amplifier Supply)
AVDD4 (Ref Buffer Supply)
DVDD
Normal Power Mode
AIDD1 (Modulator)
AIDD2 (General)5
AIDD3 (Differential Amplifier)
AIDD4 (Reference Buffer)
DIDD5
Low Power Mode
AIDD1 (Modulator)
AIDD2 (General) 5
AIDD3 (Differential Amplifier)
AIDD4 (Reference Buffer)
DIDD5
POWER DISSIPATION
Normal Power Mode
Low Power Mode
Power-Down Mode6
Test Conditions/Comments
AVDD3 = 5 V ± 5%
Voltage range at input pins: VINA+ and VINA−
On-chip differential amplifier pins: VOUT+ and VOUT−
±5%
±5%
±5%
±5%
±5%
MCLK = 40 MHz
AVDD3 = 5 V
AVDD4 = 5 V
MCLK = 40 MHz
MCLK = 40 MHz
AVDD3 = 5 V
AVDD4 = 5 V
MCLK = 40 MHz
MCLK = 40 MHz, decimate 64×
MCLK = 40 MHz, decimate 64×
PWRDWN held logic low
Specification
4.096
±1
5
2.25 to 5.25
7.3
±1
0.8 × DVDD
0.2 × DVDD
2.2
0.1
>1
125
−0.5 to +2.2
2.048
2.5
5
5
5
2.5
19
13
10
9
37
10
7
5.5
5
20
300
371
160
215
1
1 See Terminology section.
2 SNR specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
3 Output Data Rate (ODR) = [(MCLK/2)]/Decimation Rate. That is, the maximum ODR for AD7764 = [(40 MHz)/2)/64] = 312.5 kHz.
4 Tested with a 400 μA load current.
5 Tested at MCLK = 40 MHz. This current scales linearly with MCLK frequency applied.
6 Tested at 125°C.
Unit
V
μA max
pF typ
V
pF typ
μA/pin max
V min
V max
V min
V max
MΩ
kHz
V
V
V
V
V min/max
V min/max
V
mA typ
mA typ
mA typ
mA typ
mA typ
mA typ
mA typ
mA typ
mA typ
mA typ
mW typ
mW max
mW typ
mW max
mW typ
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