EVAL-AD7851CB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7851CB' PDF : 36 Pages View PDF
AD7851
Parameter
Version A1 Version K1 Unit
Test Conditions/Comments
POWER PERFORMANCE
AVDD, DVDD
IDD
Normal Mode4
Sleep Mode5
With External Clock On
With External Clock Off
Normal Mode Power Dissipation
Sleep Mode Power Dissipation
With External Clock On
With External Clock Off
4.75/5.25
17
20
600
10
300
89.25
105
52.5
4.75/5.25
17
20
600
10
300
89.25
105
52.5
V min/max
mA max
AVDD = DVDD = 4.75 V to 5.25 V. Typically
12 mA.
µA typ
µA typ
µA max
µA typ
mW max
µW typ
µW max
Full Power-Down. Power management bits
in control register set as PMGT1 = 1, PMGT0 = 0.
Partial Power-Down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
Typically 1 µA. Full Power-Down. Power
management bits in control register set as
PMGT1 = 1, PMGT0 = 0.
Partial Power-Down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
VDD = 5.25 V: Typically 63 mW; SLEEP = VDD.
VDD = 5.25 V; SLEEP = 0 V.
VDD = 5.25 V; Typically 5.25 µW; SLEEP = 0 V.
SYSTEM CALIBRATION
Offset Calibration Span6
Gain Calibration Span6
+0.05 × VREF/–0.05 × VREF V max/min Allowable Offset Voltage Span for Calibration.
+1.025 × VREF/–0.975 × VREF V max/min Allowable Full-Scale Voltage Span for Calibration.
NOTES
1Temperature ranges as follows: A Version, –40°C to +125°C; K Version, 0°C to 125°C.
2Specifications apply after calibration.
3SNR calculation includes distortion and noise components.
4All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DVDD. No load on the digital outputs. Analog inputs at AGND.
5CLKIN at DGND when external clock off. All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DVDD. No load on the digital outputs.
Analog inputs at AGND.
6The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are
not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × VREF, and the
allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF ± 0.025 × VREF). This is
explained in more detail in the Calibration section of the data sheet.
Specifications subject to change without notice.
–4–
REV. B
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