EVAL-AD7961FMCZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7961FMCZ' PDF : 24 Pages View PDF
Data Sheet
AD7961
DIGITAL INTERFACE
CONVERSION CONTROL
All analog-to-digital conversions are controlled by the CNV±
signal. This signal can be applied in the form of a CNV+/CNV−
LVDS signal, or it can be applied in the form of a 1.8 V CMOS
logic signal to the CNV+ pin when CNV− is grounded. The
conversion is initiated by the rising edge of the CNV± signal.
After the AD7961 is powered up, the first conversion result
generated is valid. The key beneficial feature of the AD7961 is
that the user can return to the acquisition phase before the end
of the conversion.
The two methods for acquiring the digital data output of the
AD7961 via the LVDS interface are described in the Echoed
Clock Interface Mode and Self Clocked Mode sections.
Echoed Clock Interface Mode
The digital operation of the AD7961 in echoed clock interface
mode is shown in Figure 35. This interface mode, requiring
only a shift register on the digital host, can be used with many
digital hosts (such as FPGA, shift register, and microprocessor).
It requires three LVDS pairs (D±, CLK±, and DCO±) between
each AD7961 and the digital host.
The clock DCO± is a buffered copy of CLK± and is synchronous
to the data, D±, which is updated on the falling edge of DCO±
(tD). By maintaining good propagation delay matching between
D± and DCO± through the board and the digital host, DCO± can
be used to latch D± with good timing margin for the shift register.
Conversions are initiated by a rising edge of the CNV± pulse.
The CNV± pulse must be returned low (≤tCNVH maximum) for
valid operation. After a conversion begins, it continues until
completion. Additional CNV± pulses are ignored during the
conversion phase. After tMSB elapses, the host begins to burst the
CLK±. Note that tMSB is the maximum time for the MSB of the
new conversion result. Use tMSB as the gating device for CLK±.
The echoed clock, DCO±, and the data, D±, are driven in phase
with D± being updated on the falling edge of DCO±; the host
uses the rising edge of DCO± to capture D±. The only require-
ment is that the 16 CLK± pulses finish before tCLKL of the next
conversion phase elapses, or the data is lost. After all 16 bits are
read, up to tMSB, D± and DCO± are driven to 0. Set CLK± to idle
low between CLK± bursts.
CNV–
CNV+
SAMPLE N
tCNVH
tCYC
SAMPLE N + 1
tACQ
ACQUISITION
tCLK
CLK–
CLK+
DCO–
tDCO
DCO+
D+
tCLKD
D–
15 16
ACQUISITION
1
2
tCLKL
15 16
ACQUISITION
1
2
3
15 16
1
2
15 16
tMSB
D1 D0
N–1 N–1
0
tD
D15
D14
N
N
D1 D0
N
N
0
Figure 35. Echoed Clock Interface Mode Timing Diagram
1
2
3
D15
N+1
D14 D13
N+1 N+1
Rev. B | Page 19 of 24
Share Link: 
