EVAL-AD7982SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7982SDZ' PDF : 26 Pages View PDF
AD7982
DIGITAL INTERFACE
Although the AD7982 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7982 is compatible with SPI, QSPI,
digital hosts, and digital signal processors (DSPs). In CS mode,
the AD7982 can use either a 3-wire or 4-wire interface. A 3-
wire interface using the CNV, SCK, and SDO signals minimizes
wiring connections useful, for instance, in isolated applications.
A 4-wire interface using the SDI, CNV, SCK, and SDO signals
allows CNV, which initiates the conversions, to be independent of
the readback timing (SDI). The 4-wire interface is useful in low
jitter sampling or simultaneous sampling applications.
When in chain mode, the AD7982 provides a daisy-chain feature
using the SDI input for cascading multiple ADCs on a single
data line similar to a shift register.
Data Sheet
The mode in which the device operates depends on the SDI
level when the CNV rising edge occurs. The CS mode is
selected if SDI is high, and the chain mode is selected if SDI is
low. The SDI hold time is such that when SDI and CNV are
connected together, the chain mode is always selected.
In either mode, the AD7982 offers the option of forcing a start
bit in front of the data bits. The start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must
timeout the maximum conversion time prior to readback.
The busy indicator feature is enabled
In the CS mode if CNV or SDI is low when the ADC
conversion ends (see Figure 31 and Figure 35).
In the chain mode if SCK is high during the CNV rising
edge (see Figure 39).
Rev. E | Page 18 of 26
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