EVAL-AD7982SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7982SDZ' PDF : 26 Pages View PDF
Data Sheet
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
CS mode, 4-wire without busy indicator is usually used when
multiple AD7982 devices are connected to an SPI-compatible
digital host.
A connection diagram example using two AD7982 devices is
shown in Figure 32, and the corresponding timing is given in
Figure 33.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase
and the subsequent data readback. If SDI and CNV are low,
SDO is driven low. Prior to the minimum conversion time, SDI
can select other SPI devices, such as analog multiplexers, but
SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator.
AD7982
When the conversion completes, the AD7982 enters the
acquisition phase and powers down. Each ADC result can be
read by bringing its SDI input low, which consequently outputs
the MSB onto SDO. The remaining data bits are then clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can capture the data, a digital
host using the SCK falling edge allows a faster reading rate,
provided it has an acceptable hold time. After the 18th SCK
falling edge or when SDI goes high (whichever occurs first), SDO
returns to high impedance and another AD7982 can be read.
CNV
ACQUISITION
tCONV
CONVERSION
tSSDICNV
SDI(CS1)
tHSDICNV
CS2
CS1
CONVERT
CNV
SDI AD7982 SDO
CNV
SDI AD7982 SDO
DIGITAL HOST
SCK
SCK
DATA IN
CLK
Figure 32. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
tCYC
tACQ
ACQUISITION
SDI(CS2)
SCK
SDO
tSCKL
tSCK
1
2
3
16
17
18
tHSDO
tEN
tSCKH
tDSDO
D17 D16 D15
D1
D0
19
20
D17 D16
34
35
36
tDIS
D1
D0
Figure 33. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Rev. E | Page 21 of 26
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