EVAL-AD7985EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7985EBZ' PDF : 28 Pages View PDF
Data Sheet
AD7985
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.1
Table 4.
Parameter
Conversion Time: CNV Rising Edge
to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width
Data Read During Conversion
Quiet Time During Acquisition from Last SCK
Falling Edge to CNV Rising Edge
SCK Period
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D15 MSB Valid
CNV or SDI High or Last SCK Falling Edge
to SDO High Impedance
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge
SCK Valid Setup Time from CNV Rising Edge
SCK Valid Hold Time from CNV Rising Edge
SDI Valid Setup Time from SCK Falling Edge
SDI Valid Hold Time from SCK Falling Edge
SDI High to SDO High
Symbol
tCONV
tACQ
tCYC
tCNVH
tDATA
tQUIET
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
Test Conditions/Comments
Turbo mode/normal mode
Turbo mode/normal mode
CS mode
Turbo mode/normal mode
CS mode
Chain mode
Min
Typ
80
400/500
10
20
9
11
3.5
3.5
2
CS mode
4
CS mode
0
Chain mode
0
Chain mode
5
Chain mode
5
Chain mode
2
Chain mode
3
Chain mode with busy indicator
Max
Unit
320/420 ns
ns
ns
ns
190/290 ns
ns
ns
ns
ns
ns
ns
4
ns
5
ns
8
ns
ns
ns
ns
ns
ns
ns
ns
15
ns
1 See Figure 2 and Figure 3 for load conditions.
500µA IOL
TO SDO
CL
20pF
1.4V
500µA IOH
Figure 2. Load Circuit for Digital Interface Timing
90% VIO
tDELAY
VIH1
VIL1
10% VIO
tDELAY
VIH1
VIL1
1MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
Figure 3. Voltage Levels for Timing
Rev. C | Page 5 of 28
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