EVAL-AD7985FMCZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7985FMCZ' PDF : 28 Pages View PDF
Data Sheet
AD7985
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7985 devices are
connected to an SPI-compatible digital host. A connection dia-
gram example using two AD7985 devices is shown in Figure 30,
and the corresponding timing is given in Figure 31.
With SDI high, a rising edge on CNV initiates a conversion,
selects CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase
and the subsequent data readback. (If SDI and CNV are low,
SDO is driven low.) Prior to the minimum conversion time,
SDI can select other SPI devices, such as analog multi-plexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator.
When the conversion is complete, the AD7985 enters the
acquisition phase and powers down. Each ADC result can be
read by bringing the SDI input low, which consequently outputs
the MSB onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided that it has an acceptable hold time. After the 16th
SCK falling edge, SDO returns to high impedance and another
AD7985 can be read.
CNV
tCONV
AQUISITION CONVERSION
CNV
SDI AD7985 SDO
CNV
SDI AD7985 SDO
CS2
CS1
CONVERT
DIGITAL HOST
SCK
SCK
DATA IN
CLK
Figure 30. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
tCYC
tACQ
AQUISITION
tSSDICNV
SDI (CS1)
tHSDICNV
tQUIET
SDI (CS2)
SCK
SDO
tSCKL
tSCK
1
2
3
14
15
16
tHSDO
tSCKH
tEN
tDSDO
D15 D14 D13
D1
D0
17
18
30
D15 D14
31
32
tDIS
D1
D0
Figure 31. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Rev. C | Page 21 of 28
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