EVAL-ADE7763EB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADE7763EB' PDF : 56 Pages View PDF
ADE7763
CURRENT SIGNAL (i(t))
0x28 51EC
0x00
0xD7 AE14
CHANNEL 1
HPF1
24
IRMSOS[11:0]
IRMS(t)
sgn 225 226 227
LPF3
+
217 216 215 0x1C 82B3
0x00
24
IRMS
Figure 45. Channel 1 RMS Signal Processing
With the specified full-scale analog input signal of 0.5 V, the ADC
produces an output code that is approximately ±2,642,412d—
see the Channel 1 ADC section. The equivalent rms value of a
full-scale ac signal is 1,868,467d (0x1C82B3). The current rms
measurement provided in the ADE7763 is accurate to within
1% for signal input between full scale and full scale/100.
Converting the register value to its equivalent in amps must be
done externally in the microprocessor using an amps/LSB
constant. To minimize noise, synchronize the reading of the
rms register with the zero crossing of the voltage input and take
the average of a number of readings.
Channel 1 RMS Offset Compensation
The ADE7763 incorporates a Channel 1 rms offset compensa-
tion register (IRMSOS). This is a 12-bit, signed register that can
be used to remove offset in the Channel 1 rms calculation. An
offset might exist in the rms calculation due to input noises that
are integrated in the dc component of V2(t). The offset calibration
allows the content of the IRMS register to be maintained at 0
when no input is present on Channel 1.
One LSB of the Channel 1 rms offset is equivalent to 32,768 LSB
of the square of the Channel 1 rms register. Assuming that the
maximum value from the Channel 1 rms calculation is
1,868,467d with full-scale ac inputs, then 1 LSB of the Channel 1
rms offset represents 0.46% of the measurement error at –60 dB
down of full scale.
IRMS = IRMS0 2 + IRMSOS × 32768
(4)
where IRMS0 is the rms measurement without offset correction.
To measure the offset of the rms measurement, two data points
are needed from nonzero input values, for example, the base
current, Ib, and Imax/100. The offset can be calculated from these
measurements.
CHANNEL 2 ADC
Channel 2 Sampling
In Channel 2 waveform sampling mode (MODE[14:13] = 1, 1
and WSMP = 1), the ADC output code scaling for Channel 2 is
not the same as it is for Channel 1. The Channel 2 waveform
sample is a 16-bit word and sign extended to 24 bits. For normal
operation, the differential voltage signal between V2P and V2N
should not exceed 0.5 V. With maximum voltage input (±0.5 V
at PGA gain of 1), the output from the ADC swings between
0x2852 and 0xD7AE (±10,322d). However, before being passed
to the waveform register, the ADC output is passed through a
single-pole, low-pass filter with a cutoff frequency of 140 Hz.
The plots in Figure 46 show the magnitude and phase response
of this filter.
0
0
60Hz, –0.73dB
–10
50Hz, –0.52dB
–2
–20
–4
50Hz, –19.7°
–30
–6
60Hz, –23.2°
–40
–8
–50
–10
–60
–12
–70
–14
–80
–16
–90
101
102
FREQUENCY (Hz)
–18
103
Figure 46. Magnitude and Phase Response of LPF1
The LPF1 has the effect of attenuating the signal. For example,
if the line frequency is 60 Hz, the signal at the output of LPF1
will be attenuated by about 8%.
|H(f)|
=
1
1
+
⎜⎛
⎜⎝
60 Hz
140 Hz
⎟⎞
⎟⎠
2
= 0.919 = −0.73 db
(5)
Note LPF1 does not affect the active power calculation. The
signal processing chain in Channel 2 is illustrated in Figure 47.
Rev. A | Page 22 of 56
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