EVAL-ADF7025DB1 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADF7025DB1' PDF : 44 Pages View PDF
ADF7025
RSSI/AGC
The RSSI is implemented as a successive compression log amp
following the baseband channel filtering. The log amp achieves
±3 dB log linearity. It also doubles as a limiter to convert the
signal-to-digital levels for the FSK demodulator. Offset
correction is achieved using a switched capacitor integrator in
feedback around the log amp. This uses the BB offset clock
divide. The RSSI level is converted for user readback and
digitally controlled AGC by an 80-level (7-bit) flash ADC. This
level can be converted to input power in dBm.
OFFSET
CORRECTION
1
A
A
A
LATCH
FSK
DEMOD
IFWR IFWR IFWR IFWR
CLK
R
RSSI
DEMOD
ADC
Figure 28. RSSI Block Diagram
Offset Correction Clock
In Register 3, the user should set the BB offset clock divide bits
R3_DB [4:5] to give an offset clock between 1 MHz and 2 MHz,
where BBOS _CLK [Hz] = XTAL/(BBOS_CLK_DIVIDE).
BBOS_CLK_DIVIDE can be set to 4, 8, or 16.
AGC Information
In Register 9, the user should select automatic gain control by
selecting Auto In R9_DB18 and Auto In R9_DB19. The user
should then program AGC Low Threshold R9_DB [4:10] and
AGC High Threshold R9_DB [11:17]. The default values for the
low and high thresholds are 30 and 70, respectively; however,
these are not the optimum settings for all operating conditions.
The recommended values for the low and high thresholds are
15 and 79, respectively. In the AGC 2 register (Register 10), the
user should program the AGC delay to be long enough to allow
the loop to settle. The default/recommended value is 10.
AGC _ Wait _ Time = AGC _ DELAY × SEQ _ CLK _ DIVIDE
XTAL
AGC Settling = AGC_Wait_Time × Number of Gain Changes
Thus, in the worst case, if the AGC loop has to go through all five
gain changes, AGC delay = 10, and SEQ_CLK = 200 kHz, then
AGC settling = 10 × 5 µs × 5 = 250 μs. Minimum AGC_Wait_Time
must be at least 25 µs.
RSSI Formula (Converting to dBm)
Input_Power [dBm] = −98 dBm + (Readback_Code +
Gain_Mode_Correction ) × 0.5
where:
Readback_Code is given by Bit RV7 to Bit RV1 in the readback
register (see the Readback Format section).
Gain_Mode_Correction is given by the values in Table 5.
LNA gain and filter gain (LG2/LG1, FG2/FG1) are also
obtained from the readback register.
Table 5. Gain Mode Correction
LNA Gain
(LG2, LG1)
Filter Gain
(FG2, FG1)
H (11)
H (10)
M (10)
H (10)
M (10)
M (01)
M (10)
L (00)
L (01)
L (00)
EL (00)
L (00)
Gain Mode Correction
0
17
53
65
90
113
These numbers are for an unmodulated tone. For a modulated
signal, the RSSI readback may have to be adjusted to get the
required accuracy. An additional factor should also be
introduced to account for losses in the front-end matching
network/antenna.
FSK DEMODULATORS ON THE ADF7025
The two FSK demodulators on the ADF7025 are
• FSK correlator/demodulator
• Linear demodulator
Select these using the Demod Select Bits R4_DB [4:5].
FSK CORRELATOR/DEMODULATOR
The quadrature outputs of the IF filter are first limited and then
fed to a pair of digital frequency correlators that perform band-
pass filtering of the binary FSK frequencies at (IF + FDEV) and
(IF − FDEV). Data is recovered by comparing the output levels
from each of the two correlators. The performance of this
frequency discriminator approximates that of a matched filter
detector, which is known to provide optimum detection in the
presence of AWGN.
FREQUENCY CORRELATOR
SLICER
I
0
Rx DATA
+
LIMITERS
Q
– FDEV
+ FDEV
–
0
Rx CLK
DB(4:13) DB(14)
DB(8:15)
Figure 29. FSK Correlator/Demodulator Block Diagram
Rev. A | Page 20 of 44
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