EVAL-ADF7025DB1 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADF7025DB1' PDF : 44 Pages View PDF
ADF7025
TIMING CHARACTERISTICS
VDD = 3 V ± 10%; VGND = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter1
Limit at TMIN to TMAX
Unit
t1
<10
ns
t2
<10
ns
t3
<25
ns
t4
<25
ns
t5
<10
ns
t6
<20
ns
t8
<25
ns
t9
<25
ns
t10
<10
ns
1 Guaranteed by design, not production tested.
TIMING DIAGRAMS
t3
SCLK
Test Conditions/Comments
SDATA to SCLK setup time
SDATA to SCLK hold time
SCLK high duration
SCLK low duration
SCLK to SLE setup time
SLE pulse width
SCLK to SREAD data valid, readback
SREAD hold time after SCLK, readback
SCLK to SLE disable time, readback
t4
t1
t2
SDATA
DB31 (MSB)
DB30
DB2
DB1
(CONTROL BIT C2)
SLE
t1
t2
SCLK
Figure 2. Serial Interface Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t6
t5
SDATA
SLE
REG7 DB0
(CONTROL BIT C1)
t3
SREAD
t8
X
RV16
RV15
t9
Figure 3. Readback Timing Diagram
t10
RV2
RV1
Rev. A | Page 7 of 44
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