ADG901/ADG902
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 1
8 RF2
CTRL 2 ADG901/ 7 GND
ADG902
GND 3 TOP VIEW 6 GND
(Not to Scale)
RF1 4
5 GND
Figure 4. 8-Lead MSOP (RM-8) and
8-Lead 3 mm × 3 mm LFCSP (CP-8 – Exposed pad tied to substrate, GND
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Description
1
VDD
Power Supply Input. These parts can be operated from 1.65 V to 2.75 V; VDD should be decoupled to GND.
2
CTRL
CMOS or LVTTL Logic Level. CTRL input should not exceed VDD.
0 → RF1 Isolated from RF2.
1 → RF1 to RF2.
3, 5, 6, 7 GND
Ground Reference Point for All Circuitry on the Part.
4
RF1
RF1 Port.
8
RF2
RF2 Port.
Table 4. Truth Table
CTRL
0
1
Signal Path
RF1 isolated from RF2
RF1 to RF2
Rev. B | Page 5 of 16