ADM1067
Parameter
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Input Low Current, IIL
SEQUENCING ENGINE TIMING
State Change Time
Min Typ
4
250
5
10
Max
1000
300
1
Unit Test Conditions/Comments
μs
μs
μs
ns
ns
μA VIN = 0
μs
1 At least one of the VH, VPn pins must be ≥ 3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested, but is supported by characterization data at initial product release.
Rev. B | Page 6 of 32