EVAL-ADM1073MEB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADM1073MEB' PDF : 24 Pages View PDF
UV (Undervoltage)
The voltage on the UV pin is compared to an internal 0.868 V
reference. For the implementation in Figure 33, the undervolt-
age level is then set as
VUV = 0.868 × (R1 + R2)/R2
If the UV pin voltage is less than 0.868 V and the comparator
trips, an internal 5 µA current sink is turned on. This pulls the
UV voltage down by
VUVHYST(PIN) = 5 µA × R1 × R2/(R1 + R2)
at the UV pin, or by
VUVHYST(SUPPLY) = 5 µA × R1
at the supply.
In this manner, the user can program the value of the voltage
hysteresis by varying the parallel impedance of the resistor
divider. The UV comparator has an internal 0.6 ms time delay
to prevent nuisance shutdowns under noisy supply conditions.
OV (Overvoltage)
The voltage on the UV pin is compared to an internal 1.93 V
reference. For the implementation in Figure 33, the overvoltage
level is then set as
VOV = 1.93 × (R3 + R4)/R3
If the OV pin voltage exceeds 1.93 V and the comparator trips,
an internal 5 µA current source is turned on. This pulls the OV
voltage up by
VOVHYST(PIN) = 5 µA × R3 × R4/(R3 + R4)
at the OV pin, or by
VOVHYST(SUPPLY) = 5 µA × R3
at the supply.
ADM1073
In this manner, the user can program the value of the voltage
hysteresis by varying the parallel impedance of the resistor
divider. The OV comparator has an internal 5 µs time delay.
If the voltage on UV or OV goes out of range (below 0.868 V on
UV or above 1.93V on OV), GATE is pulled low. If the supply
subsequently reenters the operating voltage window, the
ADM1073 restores the GATE drive.
Hysteresis must be considered when reentering the operating
window, that is, VUV must increase above
0.868 V + VUVHYST(SUPPLY)
when recovering from an undervoltage fault, and VOV must drop
below
1.93 V − VOVHYST(SUPPLY)
when recovering from an overvoltage fault for GATE to be
restored.
Alternative UV and OV Configurations
A 2-resistor or a 3-resistor implementation can also be used to
set the UV and OV levels (see Figure 34 and Figure 35).
–48V RTN
R1
OV
ADM1073
UV
R2
–48V IN
Figure 34. 2-Resistor UV/OV Implementation
–48V RTN
R1
OV
R2
ADM1073
UV
R3
–48V IN
Figure 35. 3-Resistor UV/OV Implementation
Rev. 0 | Page 17 of 24
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