EVAL-ADM1075EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-ADM1075EBZ
Analog Devices
'EVAL-ADM1075EBZ' PDF : 52 Pages View PDF
ADM1075
Data Sheet
timing cycle. The TIMER pin is pulled up with 3 μA. When the
TIMER reaches the VTIMERH threshold (1.0 V), the first portion
of the initial cycle is complete. The 100 μA current source then
pulls down the TIMER pin until it reaches VTIMERL (0.05 V). The
initial cycle duration is related to CTIMER by the following equation:
t INITIAL
=
VTIMERH × CTIMER
3 μA
+ (VTIMERH
−VTIMERL ) ×CTIMER
100 μA
For example, a 470 nF capacitor results in a power-up delay of
approximately 160 ms. Provided the UV and OV detectors are
inactive when the initial timing cycle terminates, the device is
ready to start a hot swap operation.
When the voltage across the sense resistor reaches the circuit
breaker trip voltage, VCB, the 60 µA timer pull-up current is
activated, and the gate begins to regulate the current at the current
limit. This initiates a ramp-up on the TIMER pin. If the sense
voltage falls below this circuit breaker trip voltage before the
TIMER pin reaches VTIMERH (1.0 V), the 60 µA pull-up is
disabled, and the 2 µA pull-down is enabled.
The circuit breaker trip voltage is not the same as the hot swap
sense voltage current limit. There is a small circuit breaker
offset, VCBOS, which means that the timer actually starts a short
time before the current reaches the defined current limit.
advantage of setting very low inrush currents where required by
combination of large output capacitance and FET SOA limitations.
The object of such a design is to allow a linear monotonic
power-up event without the restrictions of the system fault
timer. To achieve this, a power-up ramp is set so that the inrush
is low enough not to reach the circuit breaker current limit, or
constant power current limit. This allows power-up to continue
without the timer running. When using this method, take
separate care to ensure the power in the MOSFET during this
event meets the SOA requirements. The components labeled
RGD, CGD and CG on the gate pin in Figure 51 show the required
extra components.
0V
–48V
VIN PLIM
ADM1075
VEE GATE
CLOAD
RPLIM1
RPLIM2
RGD CGD
10Ω
D
CG
S
RSENSE
Figure 51. Required Extra Components
However, if the overcurrent condition is continuous and the
sense voltage remains above the circuit breaker trip voltage, the
60 µA pull-up remains active and the FET remains in regulation.
This allows the TIMER pin to reach VTIMERH and initiate the
GATE shutdown. The LATCH pin is pulled low immediately.
In latch-off mode, the TIMER pin is switched to the 2 µA pull-
down when it reaches the VTIMERH threshold. The LATCH pin
remains low. While the TIMER pin is being pulled down, the
hot swap controller is kept off and cannot be turned back on.
When the voltage on the TIMER pin goes below the VTIMERL
threshold, the hot swap controller can be reenabled by toggling
the UVx pin or by using the PMBus OPERATION command to
toggle the ON bit from on to off and then on again.
SETTING A LINEAR OUTPUT VOLTAGE RAMP AT
POWER-UP
The ADM1075 standard method of operation is to control a constant
power in the MOSFET during power-up into the load. This can
result in non-linear output voltage ramps and often requires
many retry attempts to charge larger load capacitances, due to
MOSFET SOA limitations. However, there is a way to configure
a single linear voltage ramp on the output which allows a constant
inrush current to be maintained. For a typical power-up using
constant power, as the output voltage increases in magnitude,
the controlled current also increases to maintain a constant power
in the pass MOSFET. This can be a challenge for maintaining
MOSFET SOA, where higher drain currents limit energy transfer
more than lower currents. However, if the output voltage is
programmed to result in a linear ramp, the inrush into the load
capacitance remains somewhat constant. This can have the
To ensure the inrush current does not approach or exceed the
active current limit level, the output voltage ramp can be set by
selecting the appropriate value for CGD as follows:
CGD = (IGATEUP/IINRUSH) × CLOAD
where IGATEUP is the gate pull-up current specified.
Add margin and tolerance as necessary to ensure a robust
design. Subtract any parasitic CGD of the MOSFETS from the
total to determine the additional external capacitance required.
The power-up ramp time can now be approximated by:
tRAMP = (VIN × CLOAD)/IINRUSH
Check the SOA of the MOSFET for conditions and the duration
of this power-up ramp.
RGD and CG are used to limit the impact of sudden transients on
the MOSFET Drain pin being coupled to the GATE pin through
CGD. RG is chosen such that IGATEUP has minimal voltage drop
impact. Typical values would be 1 K. As a rule, CG is recommended
to be about 10× the value of CGD, to a maximum of 470 nF. CG
must be minimized and must not exceed 470 nF to avoid slowing
down gate shutdown in response to severe overcurrent events.
This capacitance results in slowing down the gate ramp through
VTH and therefore the trans-conductance current ramp. This
delay must also be considered when checking SOA during
power-up into a fault. When using this method, always remove
the SS cap, and TIMER can be minimized to provide a simple
fault filtering solution.
Rev. D | Page 24 of 52
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