EVAL-ADM1192EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADM1192EBZ' PDF : 20 Pages View PDF
Data Sheet
WRITE EXTENDED COMMAND BYTE
In the write extended command byte operation, the master
device writes to one of the three extended registers of the slave
device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address, followed by the
write bit (low).
3. The addressed slave device asserts an acknowledge on SDA.
4. The master sends the register address byte. The MSB of this
byte is set to 1 to indicate an extended register write. The two
LSBs indicate which of the three extended registers are to be
written to (see Table 8). All other bits should be set to 0.
5. The slave asserts an acknowledge on SDA.
6. The master sends the extended command byte (refer to
Table 9, Table 10, and Table 11).
ADM1192
7. The slave asserts an acknowledge on SDA.
8. The master asserts a stop condition on SDA to end the
transaction.
1
2
3
4
5
6
78
S
SLAVE
ADDRESS
WA
REGISTER
ADDRESS
A
EXTENDED
COMMAND
A
P
BYTE
Figure 23. Write Extended Byte
Table 9, Table 10, and Table 11 provide the details of each
extended register.
Table 8. Extended Register Addresses
A6 A5 A4 A3 A2 A1 A0
0000001
0000010
0000011
Extended Register
ALERT_EN
ALERT_TH
CONTROL
Table 9. ALERT_EN Register Operations
Bit Default Name
Function
0
0
EN_ADC_OC1 LSB, enabled if a single ADC conversion on the I channel exceeds the threshold set in the ALERT_TH register.
1
0
EN_ADC_OC4 Enabled if four consecutive ADC conversions on the I channel exceed the threshold set in the
ALERT_TH register.
2
1
EN_OC_ALERT Enables the OC_ALERT register. If an overcurrent condition is present compared to the SETV threshold, and
the TIMER pin charges to 1.3 V, the OC_ALERT register captures and latches this condition.
3
0
EN_OFF_ALERT Enables an alert if the hot swap operation is turned off by an operation that writes the SWOFF bit high.
This allows a software override of the ALERT output and turns on a P-channel FET controlled by ALERT.
4
0
CLEAR
Clears the OC_ALERT and ADC_ALERT status bits in the status register. The value of these bits can
immediately change if the source of the alert is not cleared and the alert function is not disabled.
The CLEAR bit self-clears to 0 after the STATUS register bits are cleared.
Table 10. ALERT_TH Register Operations
Bit Default Function
[7:0] FF
The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit
value corresponds to the top eight bits of the current channel data.
Table 11. CONTROL Register Operations
Bit Default Name
Function
0
0
SWOFF
LSB, forces the ALERT pin to deassert. Can be active only if the EN_OFF_ALERT bit is high (see Table 9).
Rev. D | Page 13 of 20
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