EVAL-ADT7X20EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADT7X20EBZ' PDF : 24 Pages View PDF
Preliminary Technical Data
REGISTERS
The ADT7420 contains 14 registers:
• Nine temperature registers
• A status register
• An ID register
• A configuration register
• An address pointer register
• A software reset
All registers are eight bits wide. The temperature value registers,
the status register, and the ID register are read-only. The software
reset is a write-only register. On power-up, the address pointer
register is loaded with 0x00 and points to the temperature value
register MSB.
Table 6. ADT7420 Registers
Register
Address Description
0x00
Temperature value most significant byte
0x01
Temperature value least significant byte
0x02
Status
0x03
Configuration
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
THIGH setpoint most significant byte
THIGH setpoint least significant byte
TLOW setpoint most significant byte
TLOW setpoint least significant byte
TCRIT setpoint most significant byte
TCRIT setpoint least significant byte
THYST setpoint
ID
0x2F
Software reset
Power-On
Default
0x00
0x00
0x00
0x00
0x20 (64°C)
0x00 (64°C)
0x05 (10°C)
0x00 (10°C)
0x49 (147°C)
0x80 (147°C)
0x05 (5°C)
0xCX
0xXX
ADT7420
ADDRESS POINTER REGISTER
This register is always the first register written to during a write
to the ADT7420. It should be set to the address of the register
to which the write or read transaction is intended. Table 7
shows the register address of each register on the ADT7420.
The default value of the address pointer register is 0x00.
Table 7. Address Pointer Register
P7
P6
P5
P4
P3
ADD7 ADD6 ADD5 ADD4 ADD3
P2
ADD2
P1
ADD1
P0
ADD0
TEMPERATURE VALUE REGISTERS
The temperature value most significant byte (MSB) and tem-
perature value least significant byte (LSB) registers store the
temperature measured by the internal temperature sensor.
The temperature is stored in twos complement format with
the MSB being the temperature sign bit. When reading from
these registers, the eight MSBs (Bit 7 to Bit 15) are read first
from Register Address 0x00 and then the eight LSBs (Bit 0 to
Bit 7) are read from Register Address 0x01. Only the tempera-
ture value most significant byte (Register Address 0x00) needs to
be loaded into the address pointer register because the address
pointer autoincrements to the temperature value least signifi-
cant byte address (Register Address 0x01).
Bit 0 to Bit 2 are event alarm flags for TCRIT, THIGH, and TLOW. When
the ADC is configured to convert the temperature to a 16-bit
digital value, then Bit 0 to Bit 2 are no longer used as flag bits
and are instead used as the LSB bits for the extended digital value.
Table 8. Temperature Value MSB Register (Register Address 0x00)
Bit
Default Value
Type Name Description
[8:14]
0000000
R
Temp
Temperature value in twos complement format
15
0
R
Sign
Sign bit, indicates if the temperature value is negative or positive
Table 9. Temperature Value LSB Register (Register Address 0x01)
Default
Bit Value
Type Name
Description
0
0
R
TLOW flag/LSB0 Flags a TLOW event if the configuration register, Register Address 0x03[7] = 0 (13-bit
resolution). When the temperature value is below TLOW, this bit it set to 1.
Contains the Least Significant Bit 0 of the 15-bit temperature value if the configuration
register, Register Address 0x03[7] = 1 (16-bit resolution).
1
0
R
THIGH flag/LSB1 Flags a THIGH event if the configuration register, Register Address 0x03[7] = 0 (13-bit
resolution). When the temperature value is above THIGH, this bit it set to 1.
Contains the Least Significant Bit 1 of the 15-bit temperature value if the configuration
register, Register Address 0x03[7] = 1 (16-bit resolution).
2
0
R
TCRIT flag/LSB2 Flags a TCRIT event if the configuration register, Register Address 0x03[7] = 0 (13-bit
resolution). When the temperature value exceeds TCRIT, this bit it set to 1.
Contains the Least Significant Bit 2 of the 15-bit temperature value if the configuration
register, Register Address 0x03[7] = 1 (16-bit resolution).
[3:7] 00000
R
Temp
Temperature value in twos complement format.
Rev. PrA | Page 13 of
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