EVAL-ADT7X20EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADT7X20EBZ' PDF : 24 Pages View PDF
Preliminary Technical Data
THIGH SETPOINT REGISTERS
The THIGH setpoint MSB and THIGH setpoint LSB registers store
the overtemperature limit value. An overtemperature event
occurs when the temperature value stored in the temperature
value register exceeds the value stored in this register. The INT
pin is activated if an overtemperature event occurs. The temper-
ature is stored in twos complement format with the MSB being
the temperature sign bit.
When reading from this register, the eight MSBs (Bit 15 to Bit 8)
are read first from Register Address 0x04 and then the eight
LSBs (Bit 7 to Bit 0) are read from Register Address 0x05. Only
Register Address 0x04 (THIGH setpoint MSB) needs to be loaded
into the address pointer register because the address pointer
autoincrements to Register Address 0x05 (THIGH setpoint LSB).
The default setting for the THIGH setpoint is 64°C.
TLOW SETPOINT REGISTERS
The TLOW setpoint MSB and TLOW setpoint LSB registers store
the undertemperature limit value. An undertemperature event
occurs when the temperature value stored in the temperature
value register is less than the value stored in this register. The
INT pin is activated if an undertemperature event occurs. The
temperature is stored in twos complement format with the MSB
being the temperature sign bit.
ADT7420
When reading from this register, the eight MSBs (Bit 15 to
Bit 8) are read first from Register Address 0x06 and then the
eight LSBs (Bit 7 to Bit 0) are read from Register Address 0x07.
Only Register Address 0x06 (TLOW setpoint MSB) needs to be
loaded into the address pointer register as the address pointer
autoincrements to Register Address 0x07 (TLOW setpoint LSB).
The default setting for the TLOW setpoint is 10°C.
TCRIT SETPOINT REGISTERS
The TCRIT setpoint MSB and TCRIT setpoint LSB registers store
the critical overtemperature limit value. A critical overtempe-
rature event occurs when the temperature value stored in the
temperature value register exceeds the value stored in this
register. The CT pin is activated if a critical overtemperature
event occurs. The temperature is stored in twos complement
format with the MSB being the temperature sign bit.
When reading from this register, the eight MSBs (Bit 15 to Bit 8)
are read first from Register Address 0x08 and then the eight
LSBs (Bit 7 to Bit 0) are read from Register Address 0x09. Only
Register Address 0x08 (TCRIT setpoint MSB) needs to be loaded
into the address pointer register because the address pointer
autoincrements to Register Address 0x09 (TCRIT setpoint LSB).
The default setting for the TCRIT limit is 147°C.
Table 12. THIGH Setpoint MSB Register (Register Address 0x04)
Bit
Default Value Type Name
Description
[15:8]
0x20
R/W THIGH MSB MSBs of the overtemperature limit, stored in twos complement format.
Table 13. THIGH Setpoint LSB Register (Register Address 0x05)
Bit
Default Value Type Name Description
[7:0]
0x00
R/W THIGH LSB LSBs of the overtemperature limit, stored in twos complement format.
Table 14. TLOW Setpoint MSB Register (Register Address 0x06)
Bit
Default Value Type Name
Description
[15:8]
0x05
R/W TLOW MSB MSBs of the undertemperature limit, stored in twos complement format.
Table 15. TLOW Setpoint LSB Register (Register Address 0x07)
Bit
Default Value Type Name
Description
[7:0]
0x00
R/W TLOW LSB LSBs of the undertemperature limit, stored in twos complement format.
Table 16. TCRIT Setpoint MSB Register (Register Address 0x08)
Bit
Default Value
Type Name
Description
[15:8]
0x49
R/W TCRIT MSB MSBs of the critical overtemperature limit, stored in twos complement format.
Table 17. TCRIT Setpoint LSB Register (Register Address 0x09)
Bit
Default Value Type Name
Description
[7:0]
0x80
R/W TCRIT LSB LSBs of the critical overtemperature limit, stored in twos complement format.
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