EVAL-ADUC814QSP View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADUC814QSP' PDF : 72 Pages View PDF
MEMORY ORGANIZATION
The ADuC814 does not have Port 0 and Port 2 pins and
therefore does not support external program or data memory
interfaces. The device executes code from the internal 8-kByte
Flash/EE program memory. This internal code space can be
programmed via the UART serial port interface while the device
is in-circuit. The program memory space of the ADuC814 is
shown in Figure 18.
PROGRAM MEMORY SPACE
READ-ONLY
1FFFH
INTERNAL
8 kBYTE
FLASH/EE
PROGRAM
MEMORY
0000H
Figure 18. Program Memory Map
The data memory address space consists of internal memory
only. The internal memory space is divided into four physically
separate and distinct blocks, namely the lower 128 bytes of
RAM, the upper 128 bytes of RAM, the 128 bytes of special
function register (SFR) area, and a 640-byte Flash/EE data
memory. While the upper 128 bytes of RAM and the SFR area
share the same address locations, they are accessed through
different addressing modes.
The lower 128 bytes of data memory can be accessed through
direct or indirect addressing, the upper 128 bytes of RAM can
be accessed through indirect addressing, and the SFR area is
accessed through direct addressing.
Also, as shown in Figure 19, an additional 640 bytes of Flash/EE
data memory are available to the user and can be accessed
indirectly via a group of control registers mapped into the SFR
area. Access to the Flash/EE data memory is discussed in detail
later as part of the Flash/EE Memory section.
ADuC814
DATA MEMORY SPACE
READ/WRITE
9FH
(PAGE 159)
640 BYTES
FLASH/EE DATA
MEMORY
ACCESSED
INDIRECTLY
VIA SFR
CONTROL REGISTERS
00H
(PAGE 0)
INTERNAL
DATA MEMORY
SPACE
FFH
ACCESSIBLE
UPPER
128
BY
INDIRECT
ADDRESSING
ONLY
80H
7FH ACCESSIBLE
LOWER
128
BY
DIRECT
AND INDIRECT
ADDRESSING
00H
SPECIAL
FUNCTION
REGISTERS
ACCESSIBLE
BY DIRECT
ADDRESSING
ONLY
FFH
80H
Figure 19. Data Memory Map
The lower 128 bytes of internal data memory are mapped as
shown in Figure 20. The lowest 32 bytes are grouped into four
banks of eight registers addressed as R0 to R7. The next 16 bytes
(128 bits), locations 20H to 2FH above the register banks, form
a block of directly addressable bit locations at bit addresses 00H
through 7FH. The stack can be located anywhere in the internal
memory address space, and the stack depth can be expanded up
to 256 bytes.
30H
BANKS
SELECTED
VIA
20H
BITS IN PSW
11
18H
10
10H
01
08H
00
00H
7FH
GENERAL-PURPOSE
AREA
2FH
BIT-ADDRESSABLE
BIT ADDRESSES
1FH
17H
0FH
07H
FOUR BANKS OF EIGHT
REGISTERS
R0 R7
RESET VALUE OF
STACK POINTER
Figure 20. Lower 128 Bytes of Internal Data Memory
RESET initializes the stack pointer to location 07H and incre-
ments it once to start from location 08H, which is also the first
register (R0) of Register Bank 1. If more than one register bank
is being used, the stack pointer should be initialized to an area
of RAM not used for data storage.
Rev. A | Page 17 of 72
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