EVAL-ADUC814QSP View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADUC814QSP' PDF : 72 Pages View PDF
ADuC814
ADCCON3 (ADC CONTROL SFR 3)
The ADCCON3 register controls the operation of various calibration modes as well as giving an indication of ADC busy status.
SFR Address
F5H
SFR Power-On Default 00H
BUSY
GNCLD
AVGS1
AVGS0
OFCLD
MODCAL
TYPECAL
SCAL
Table 8. ADCCON3 SFR Bit Designations
Bit No. Name
Description
7
BUSY
ADC Busy Status Bit.
BUSY is a read-only status bit that is set during a valid ADC conversion or calibration cycle.
Busy is automatically cleared by the core at the end of a conversion or calibration cycle.
6
GNCLD
Gain Calibration Disable Bit.
This bit enables/disables the gain calibration coefficients from affecting the ADC results.
Set to 0 to enable gain calibration coefficient
Set to 1 to disable gain calibration coefficient.
5
AVGS1
Number of Averages Selection Bits.
4
AVGS0
This bit selects the number of ADC readings averaged for each bit decision during a calibration cycle.
AVGS1 AVGS0 Number of Averages
0
0
15
0
1
1
1
0
31
1
1
63
3
OFCLD
Offset Calibration Disable Bit.
This bit enables/disables the offset calibration coefficients from affecting the ADC results.
Set to 0 to enable offset calibration coefficient.
Set to 1 to disable the offset calibration coefficient
2
MODCAL Calibration Mode Select Bit.
This bit should be set to 1 for all calibration cycles.
1
TYPECAL Calibration Type Select Bit.
This bit selects between offset (zero-scale) and gain (full-scale) calibration.
Set to 0 for offset calibration.
Set to 1 for gain calibration.
0
SCAL
Start Calibration Cycle Bit.
When set, this bit starts the selected calibration cycle.
It is automatically cleared when the calibration cycle is completed.
Rev. A | Page 24 of 72
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