EVAL-ADUC814QSP View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADUC814QSP' PDF : 72 Pages View PDF
ON-CHIP PLL
The ADuC814 is intended for use with a 32.768 kHz watch
crystal. An on-board PLL locks onto a multiple (512) of this
32.768kHz frequency to provide a stable 16.777216 MHz clock
for the system. The core can operate at this frequency or at
binary submultiples of it to allow power saving in cases where
maximum core performance is not required. The default core
clock is the PLL clock divided by 8 (2CD = 23) or 2.097152 MHz.
The PLL is controlled via the PLLCON special function register.
PLLCON
SFR Address
Power-On Default
Bit Addressable
ADuC814
PLL Control Register
D7H
03H
No
OSC_PD
LOCK
---
---
FINT
CD2
CD1
CD0
Table 13. PLLCON SFR Bit Designations
Bit No. Name Description
7
OSC_PD Oscillator Power-Down Bit.
Set by the user to halt the 32 kHz oscillator in power-down mode.
Cleared by the user to enable the 32 kHz oscillator in power-down mode. This feature allows the oscillator to
continue clocking the TIC even in power-down mode.
6
LOCK
PLL Lock Bit. This is a read-only bit.
Set automatically at power-on to indicate that the PLL loop is correctly tracking the crystal clock. If the external
crystal becomes subsequently disconnected, the PLL rails and the core halts.
Cleared automatically at power-on to indicate that the PLL is not correctly tracking the crystal clock. This may be due
to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output is 16.78 MHz ± 20%.
5
---
Reserved. Should be written with 0.
4
---
Reserved. Should be written with 0.
3
FINT
Fast Interrupt Response Bit.
Set by the user to enable the response to any interrupt to be executed at the fastest core clock frequency, regardless
of the configuration of the CD2–CD0 bits (see below). Once user code has returned from an interrupt, the core
resumes code execution at the core clock selected by the CD2–CD0 bits.
Cleared by the user to disable the fast interrupt response feature.
2
CD2
CPU (Core Clock) Divider Bits.
1
CD1
This number determines the frequency at which the microcontroller core operates.
0
CD0
CD2 CD1 CD0 Core Clock Frequency (MHz)
0
0
0
16.777216
0
0
1
8.388608
0
1
0
4.194304
0
1
1
2.097152 (Default Core Clock Frequency)
1
0
0
1.048576
1
0
1
0.524288
1
1
0
0.262144
1
1
1
0.131072
Rev. A | Page 37 of 72
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