EVAL-ADV7183BEB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADV7183BEB' PDF : 104 Pages View PDF
ADV7183A
Drive Strength Selection (Clock)
DR_STR_C[1:0] Address 0x0E [3:2]
The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
refer to the following sections:
• Drive Strength Selection (Sync)
• Drive Strength Selection (Data)
Table 21. DR_STR Function
DR_STR[1:0]
Description
00
Low drive strength (1×).
01 (default)
Medium low drive strength (2×).
10
Medium high drive strength (3×).
11
High drive strength (4×).
Drive Strength Selection (Sync)
DR_STR_S[1:0] Address 0x0E [1:0]
The DR_STR_S[1:0] bits allow the user to select the strength of
the synchronization signals with which HS, VS, and F are
driven. For more information, refer to the following sections:
• Drive Strength Selection (Clock)
• Drive Strength Selection (Data)
Table 22. DR_STR Function
DR_STR[1:0]
Description
00
Low drive strength (1×).
01 (default)
Medium low drive strength (2×).
10
Medium high drive strength (3×).
11
High drive strength (4×).
Enable Subcarrier Frequency Lock Pin
EN_SFL_PIN Address 0x04 [1]
The EN_SFL_PIN bit enables the output of subcarrier lock
information (also known as GenLock) from the ADV7183A to
an encoder in a decoder/encoder back-to-back arrangement.
Table 23. EN_SFL_PIN
EN_SFL_PIN Description
0 (default) Subcarrier frequency lock output is disabled.
1
Subcarrier frequency lock information is
presented on the SFL pin.
Polarity LLC Pin
PCLK Address 0x37 [0]
The polarity of the clock leaving the ADV7183A via the LLC1
and LLC2 pins can be inverted using the PCLK bit.
Changing the polarity of the LLC clock output may be
necessary to meet the setup-and-hold time expectations of
follow-on chips.
This bit also inverts the polarity of the LLC2 clock.
Table 24. PCLK Function
PCLK
Description
0
Invert LLC output polarity.
1 (default)
LLC output polarity normal (as per the Timing
Diagrams)
Rev. B | Page 18 of 104
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