EVAL-ADV7183BEB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADV7183BEB' PDF : 104 Pages View PDF
VBI DATA DECODE
The following low data rate VBI signals can be decoded by the
ADV7183A:
• Wide screen signaling (WSS)
• Copy generation management systems (CGMS)
• Closed captioning (CCAP)
• EDTV
• Gemstar 1×- and 2×-compatible data recovery
The presence of any of the above signals is detected and, if
applicable, a parity check is performed. The result of this testing
is contained in a confidence bit in the VBI Info[7:0] register.
Users are encouraged to first examine the VBI Info register
before reading the corresponding data registers. All VBI data
decode bits are read-only.
All VBI data registers are double-buffered with the field signals.
This means that data is extracted from the video lines and
appears in the appropriate I2C registers with the next field
transition. They are then static until the next field.
The user should start an I2C read sequence with VS by first
examining the VBI Info register. Then, depending on what data
was detected, the appropriate data registers should be read.
The data registers are filled with decoded VBI data even if their
corresponding detection bits are low; it is likely that bits within
the decoded data stream are wrong.
Notes
• The closed captioning data (CCAP) is available in the I2C
registers, and is also inserted into the output video data
stream during horizontal blanking.
• The Gemstar-compatible data is not available in the I2C
registers, and is inserted into the data stream only during
horizontal blanking.
WSSD Wide Screen Signaling Detected, Address 0x90 [0]
Logic 1 for this bit indicates that the data in the WSS1 and
WSS2 registers is valid.
The WSSD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the data transmitted.
Table 137. WSSD Function
WSSD Description
0
No WSS detected. Confidence in decoded data is low.
1
WSS detected. Confidence in decoded data is high.
ADV7183A
CCAPD Closed Caption Detected, Address 0x90 [1]
A Logic 1 for this bit indicates that the data in the CCAP1 and
CCAP2 registers is valid.
The CCAPD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the data transmitted.
Table 138. CCAPD Function
CCAPD
Description
0
No CCAP signals detected. Confidence in
decoded data is low.
1
CCAP sequence detected. Confidence in
decoded data is high.
EDTVD EDTV Sequence Detected, Address 0x90 [2]
A Logic 1 for this bit indicates that the data in the EDTV1, 2, 3
registers is valid.
The EDTVD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the data transmitted.
Table 139. EDTVD Function
EDTVD
Description
0
No EDTV sequence detected. Confidence in
decoded data is low.
1
EDTV sequence detected. Confidence in
decoded data is high.
CGMSD CGMS-A Sequence Detected, Address 0x90 [3]
Logic 1 for this bit indicates that the data in the CGMS1, 2, 3
registers is valid. The CGMSD bit goes high if a valid CRC
checksum has been calculated from a received CGMS packet.
Table 140. CGMSD Function
CGMSD
Description
0
No CGMS transmission detected. Confidence low.
1
CGMS sequence decoded. Confidence high.
CRC_ENABLE CRC CGMS-A Sequence, Address 0xB2 [2]
For certain video sources, the CRC data bits may have an
invalid format. In such circumstances, the CRC checksum
validation procedure can be disabled. The CGMSD bit goes
high if the rising edge of the start bit is detected within a time
window.
Table 141. CRC_ENABLE Function
CRC_ENABLE Description
0
No CRC check performed. The CGMSD bit goes
high if the rising edge of the start bit is detected
within a time window.
1 (default)
Use CRC checksum to validate the CGMS-A
sequence. The CGMSD bit goes high for a valid
checksum. ADI recommended setting.
Rev. B | Page 51 of 104
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