EVAL-ADV739XFEZ View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

EVAL-ADV739XFEZ

Low Power, Chip Scale, 10-Bit SD/HD Video Encoder

Analog Devices 

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ADV7390/ADV7391/ADV7392/ADV7393

Data Sheet

DIGITAL TIMING SPECIFICATIONS—1.8 V

VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V.

All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.

Table 10.

Parameter

VIDEO DATA AND VIDEO CONTROL PORT2, 3

Data Input Setup Time, t114

Data Input Hold Time, t124

Control Input Setup Time, t114

Control Input Hold Time, t124

Control Output Access Time, t134

Control Output Hold Time, t144

PIPELINE DELAY5

SD1

CVBS/Y-C Outputs (2×)

CVBS/Y-C Outputs (8×)

CVBS/Y-C Outputs (16×)

Component Outputs (2×)

Component Outputs (8×)

Component Outputs (16×)

ED1

Component Outputs (1×)

Component Outputs (4×)

Component Outputs (8×)

HD1

Component Outputs (1×)

Component Outputs (2×)

Component Outputs (4×)

RESET CONTROL

RESET Low Time

Conditions1

Min Typ Max

SD

1.4

ED/HD-SDR

1.9

ED/HD-DDR

1.9

ED (at 54 MHz)

1.6

SD

1.4

ED/HD-SDR

1.5

ED/HD-DDR

1.5

ED (at 54 MHz)

1.3

SD

1.4

ED/HD-SDR or ED/HD-DDR

1.2

ED (at 54 MHz)

1.0

SD

1.4

ED/HD-SDR or ED/HD-DDR

1.0

ED (at 54 MHz)

1.0

SD

13

ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)

12

SD

4.0

ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 5.0

SD oversampling disabled

SD oversampling enabled

SD oversampling enabled

SD oversampling disabled

SD oversampling enabled

SD oversampling enabled

ED oversampling disabled

ED oversampling enabled

ED oversampling enabled

HD oversampling disabled

HD oversampling enabled

HD oversampling enabled

68

79

67

78

69

84

41

49

46

40

42

44

100

1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.

2 Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.

3 Video control: HSYNC and VSYNC.

4 Guaranteed by characterization.

5 Guaranteed by design.

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Clock cycles

Clock cycles

Clock cycles

Clock cycles

Clock cycles

Clock cycles

Clock cycles

Clock cycles

Clock cycles

Clock cycles

Clock cycles

Clock cycles

ns

Rev. G | Page 10 of 108

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