Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
BALL A1 CORNER
1
2
3
4
5
A RSET HSYNC
VDD
P0
VDD_IO
VDD_IO 1
P2 2
P3 3
P4 4
VDD 5
DGND 6
P5 7
P6 8
PIN 1
INDICATOR
ADV7390/
ADV7391
TOP VIEW
(Not to Scale)
24 RSET
23 COMP
22 DAC 1
21 DAC 2
20 DAC 3
19 VAA
18 AGND
17 PVDD
B DAC1 VSYNC SFL
P1
P2
C VAA COMP DGND
P3
P4
D AGND GND_IO RESET
VDD
DGND
E PVDD EXT_LF ALSB
P5
P6
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO ANALOG GROUND (AGND).
Figure 18. ADV7390/ADV7391 Pin Configuration
F PGND SDA SCL CLKIN P7
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 20. ADV7390BCBZ-A Pin Configuration
VDD_IO 1
P4 2
P5 3
P6 4
VPDD7
5
6
DGND 7
P8 8
P9 9
P10 10
PIN 1
INDICATOR
ADV7392/
ADV7393
TOP VIEW
(Not to Scale)
30 RSET
29 COMP
28 DAC 1
27 DAC 2
26 DAC 3
25
24
VAAGAND
23
22
21
PVDD
EXT_LF
PGND
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO ANALOG GROUND (AGND).
Figure 19. ADV7392/ADV7393 Pin Configuration
Table 15. Pin Function Descriptions
ADV7390/
ADV7391
9 to 7, 4 to 2,
31, 30
13
Pin No.
ADV7392/
ADV7393
18 to 15, 11 to
8, 5 to 2, 39 to
37, 34
19
ADV7390
WLCSP
F5, E5, E4, C5,
C4, B5, B4, A4
F4
Mnemonic
P7 to P0
P15 to P0
CLKIN
27
33
A2
HSYNC
26
32
B2
VSYNC
25
31
B3
SFL
Input/
Output
I
I
Description
8-Bit Pixel Port (P7 to P0). P0 is the LSB. See Table 35 for
input modes (ADV7390/ADV7391).
16-Bit Pixel Port (P15 to P0). P0 is the LSB. See Table 36 for
input modes (ADV7392/ADV7393).
I
Pixel Clock Input for HD (74.25 MHz), ED1 (27 MHz or 54 MHz),
or SD (27 MHz).
I/O
Horizontal Synchronization Signal. This pin can also be
configured to output an SD, ED, or HD horizontal
synchronization signal. See the External Horizontal and
Vertical Synchronization Control section.
I/O
Vertical Synchronization Signal. This pin can also be
configured to output an SD, ED, or HD vertical
synchronization signal. See the External Horizontal and
Vertical Synchronization Control section.
I/O
Subcarrier Frequency Lock (SFL) Input.
Rev. G | Page 19 of 108