EVAL-ADV739XFEZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-ADV739XFEZ' PDF : 108 Pages View PDF
Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
Table 28. Register 0x84 to Register 0x87
SR7 to
SR0 Register
Bit Description
0x84
SD Mode
Register 4
Reserved
SD SFL/SCR/TR mode select
SD active video length
SD chroma
SD burst
SD color bars
SD luma/chroma swap
0x86
SD Mode
Register 5
NTSC color subcarrier adjust (delay from
the falling edge of output HSYNC pulse to
the start of color burst)
0x87
SD Mode
Register 6
Reserved
SD EIA/CEA-861B synchronization
compliance
Reserved
SD horizontal/vertical counter mode1
SD RGB color swap2
SD luma and color scale control
SD luma scale saturation
SD hue adjust
SD brightness
SD luma SSAF gain
SD input standard autodetection
Reserved
SD RGB input enable2
Bit Number
Reset
7 6 5 4 3 2 1 0 Register Setting
Value
0
0x00
00
Disabled.
11
SFL mode enabled.
0
720 pixels.
1
710 (NTSC), 702 (PAL).
0
Chroma enabled.
1
Chroma disabled.
0
Enabled.
1
Disabled.
0
Disabled.
1
Enabled.
0
DAC 2 = luma, DAC 3 = chroma.
1
DAC 2 = chroma, DAC 3 = luma.
0 0 5.17 μs.
0x02
0 1 5.31 μs.
1 0 5.59 μs (must be set for
Macrovision compliance).
1 1 Reserved.
0
0
Disabled.
1
Enabled.
00
0
Update field/line counter.
1
Field/line counter free running.
0
Normal.
1
Color reversal enabled.
0 Disabled.
0x00
1 Enabled.
0
Disabled.
1
Enabled.
0
Disabled.
1
Enabled.
0
Disabled.
1
Enabled.
0
Disabled.
1
Enabled.
0
Disabled.
1
Enabled.
0
0 must be written to this bit.
0
SD YCrCb input.
1
SD RGB input.
1 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
2 Available on the ADV7392/ADV7393 (40-pin devices) only.
Rev. G | Page 39 of 108
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