EVAL-CED1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-CED1Z' PDF : 28 Pages View PDF
AD7626
TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.37 V to 2.63 V; REF = 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Time Between Conversions1
CNV High Time
CNV to D (MSB) Ready
CNV to Last CLK (LSB) Delay
CLK Period2
CLK Frequency
CLK to DCO Delay (Echoed-Clock Mode)
DCO to D Delay (Echoed-Clock Mode)
CLK to D Delay
Symbol
tCYC
tCNVH
tMSB
tCLKL
tCLK
fCLK
tDCO
tD
tCLKD
Min Typ Max
100
10,000
10
40
100
72
3.33 4
(tCYC − tMSB + tCLKL)/n
250 300
0
4
7
0
1
0
4
7
Unit
ns
ns
ns
ns
ns
MHz
ns
ns
ns
1 The maximum time between conversions is 10,000 ns. If CNV± is left idle for a time greater than the maximum value of tCYC, the subsequent conversion result is invalid.
2 For the maximum CLK period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) to be read giving the maximum CLK±
frequency that can be used for a given conversion CNV frequency. In echoed-clock interface mode, n = 16; in self-clocked interface mode, n = 18.
Rev. A | Page 5 of
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