EVAL-CED1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-CED1Z' PDF : 28 Pages View PDF
AD7679
MASTER SERIAL INTERFACE
Internal Clock
The AD7679 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7679 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. Figure 38 and Figure 39 show
the detailed timing diagrams of these two modes.
Usually, because the AD7679 is used with a fast throughput, the
mode master read during conversion is the most recommended
serial mode.
In Read during Conversion mode, the serial clock and data
toggle at appropriate instants, minimizing potential
feedthrough between digital activity and critical conversion
decisions.
In Read after Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns low after the 18 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
CS, RD
EXT/INT = 0
t3
CNVST
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
BUSY
SYNC
SCLK
SDOUT
t28
t30
t29
t14
t18
t19
t20
t21
t24
1
2
3
16
17
18
t15
X
D17
D16
t16
t22
t23
D2
D1
D0
Figure 38. Master Serial Data Timing for Reading (Read after Convert)
t25
t26
t27
03085-0-040
Rev. A | Page 21 of 28
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