AD7622
1 See the Conversion Control section.
2 All timings for wideband warp mode are the same as warp mode.
3 In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
4 See the Digital Interface section and the RESET section.
5 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
6 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
DIVSCLK[0]
Symbol
SYNC to SCLK First Edge Delay Minimum
t18
Internal SCLK Period Minimum
t19
Internal SCLK Period Maximum
t19
Internal SCLK High Minimum
t20
Internal SCLK Low Minimum
t21
SDOUT Valid Setup Time Minimum
t22
SDOUT Valid Hold Time Minimum
t23
SCLK Last Edge to SYNC Delay Minimum
t24
BUSY High Width Maximum
Warp Mode
t28
Normal Mode
t28
0
0
1
1
0
1
0
1
Unit
3
3
3
3
ns
8
16
32
64
ns
20
40
60
140
ns
2
8
16
32
ns
2
8
16
32
ns
1
5
15
5
ns
0
0.5
10
28
ns
0
0.5
9
26
ns
0.64
0.92
1.47
2.57
μs
0.76
1.04
1.59
2.69
μs
500µA
IOL
TO OUTPUT
PIN CL
50pF
1.4V
500µA
IOH
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 3. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF
0.8V
tDELAY
2V
0.8V
2V
tDELAY
2V
0.8V
Figure 4. Voltage Reference Levels for Timing
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