EVAL-SDP-CB1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-SDP-CB1Z' PDF : 35 Pages View PDF
Data Sheet
DRIVER AMPLIFIER CHOICE
Although the AD7091R-5 is easy to drive, a driver amplifier
must meet the following requirements:
• Keep the noise generated by the driver amplifier as low as
possible to preserve the SNR and transition noise performance
of the AD7091R-5. The noise from the driver is filtered by
the one-pole, low-pass filter of the AD7091R-5 analog input
circuit, made by R1 and C2, or by the external filter, if one
is used. Because the typical noise of the AD7091R-5 is 350 µV
rms, the SNR degradation due to the amplifier is
SNR LOSS
=
20
log
350
350 2
+
π
2
f −3dB (NeN ) 2
where:
f−3dB is the input bandwidth, in megahertz, of the AD7091R-5
(1.5 MHz), or the cutoff frequency of the input filter, if one
is used.
N is the noise gain of the amplifier (for example, gain = 1
in a buffered configuration; see Figure 37).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
• For ac applications, the driver must have a THD
performance that is commensurate with the AD7091R-5.
• If a buffer is placed between MUXOUT and ADCIN, the driver
amplifier and the AD7091R-5 analog input circuit must
settle for a full-scale step onto the capacitor array at a 12-bit
level (0.0244%, 244 ppm). In an amplifier data sheet,
settling at 0.1% to 0.01% is more commonly specified and
may differ significantly from the settling time at a 12-bit
level. Be sure to verify the amplifier settling time before
driver selection.
Table 7. Recommended Driver Amplifiers
Product Description1
ADA4805-1 Low noise, low power, wide bandwidth amplifier
AD8031 Low voltage, low power, single channel amplifier
AD8032 Low voltage, low power, dual channel amplifier
AD8615 Low frequency, low voltage amplifier
1 For the latest recommended ADC driver products, see the AD7091R-5
product page.
AD7091R-5
TYPICAL CONNECTION DIAGRAM
Figure 37 and Figure 38 show typical connection diagrams for the
AD7091R-5.
Connect a positive power supply in the 2.7 V to 5.25 V range to
the VDD pin. The typical values for the VDD decoupling capacitors
are 100 nF and 10 µF. Place these capacitors as close as possible
to the device pins. Take care to decouple the REFIN/REFOUT pin
to achieve specified performance. The typical value for the
REFIN/REFOUT capacitor is 2.2 µF, which provides an analog input
range of 0 V to VREF. The typical value for the regulator bypass
(REGCAP) decoupling capacitor is 1 µF. The voltage applied to the
VDRIVE input controls the voltage of the serial interface; therefore,
connect this pin to the supply voltage of the microprocessor. Set
VDRIVE in the 1.8 V to 5.25 V range. The typical values for the
VDRIVE decoupling capacitors are 100 nF and 10 µF. The 16-bit
conversion result (3 address bits, 1 alert bit, and 12 data bits) is
output in 2 bytes with the most significant byte (MSBs)
presented first.
When an externally applied reference is required, disable the
internal reference using the configuration register. Choose an
externally applied reference voltage in the range of 1.0 V to VDD
and connect it to the REFIN/REFOUT pin.
For applications where power consumption is a concern, use the
power-down mode of the ADC to improve power performance.
See the Modes of Operation section for additional details.
Rev. A | Page 17 of 34
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