EVAL-SDP-CB1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-SDP-CB1Z' PDF : 35 Pages View PDF
Data Sheet
AD7091R-5
I2C TIMING SPECIFICATIONS
All values measured with the input filtering enabled. CB refers to the capacitive load on the bus line, with rise time and fall time measured
between 0.3 × VDRIVE and 0.7 × VDRIVE (see Figure 2). VDD = 2.7 V to 5.25 V, VDRIVE = 1.8 V to 5.25 V, VREF = 2.5 V internal/external, TA =
TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
fSCL
t1
t2
t3
t41
t5
t6
t7
t8
t9
t10
t11
t11A
t12
tSP
tRESETPW
tRESET_DELAY
Limit at TMIN, TMAX
Min
Typ Max
100
400
4
0.6
4.7
1.3
250
100
0
3.45
0
0.9
4.7
0.6
4
0.6
4.7
1.3
4
0.6
1000
20 + 0.1CB
300
300
20 + 0.1CB
300
1000
20 + 0.1CB
300
1000
20 + 0.1CB
300
300
20 + 0.1CB
300
0
50
10
50
Unit Description
kHz Serial clock frequency, standard mode
kHz Fast mode
µs SCL high time, standard mode
µs Fast mode
µs SCL low time, standard mode
µs Fast mode
ns Data setup time, standard mode
ns Fast mode
µs Data hold time, standard mode
µs Fast mode
µs Setup time for a repeated start condition, standard mode
µs Fast mode
µs Hold time for a repeated start condition, standard mode
µs Fast mode
µs Bus-free time between a stop and a start condition, standard mode
µs Fast mode
µs Setup time for a stop condition, standard mode
µs Fast mode
ns Rise time of the SDA signal, standard mode
ns Fast mode
ns Fall time of the SDA signal, standard mode
ns Fast mode
ns Rise time of the SCL signal, standard mode
ns Fast mode
ns Rise time of the SCL signal after a repeated; not shown in Figure 2, standard mode
ns Start condition and after an acknowledge bit, fast mode
ns Fall time of the SCL signal, standard mode
ns Fast mode
ns Pulse width of the suppressed spike; not shown in Figure 2, fast mode
ns RESET pulse width (see Figure 35)
ns RESET pulse delay upon power-up (see Figure 35)
1 A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
t11
t12
t2
t6
SCL
t6
t4
SDA
t7
P
S
S = START CONDITION
P = STOP CONDITION
t3
t1
t5
t10
S
Figure 2. 2-Wire Serial Interface Timing Diagram
t8
t9
P
Rev. A | Page 5 of 34
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