EVAL-SDP-CH1Z View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-SDP-CH1Z' PDF : 28 Pages View PDF
TYPICAL CONNECTION DIAGRAM
AD7626
V+
ADR434 8
ADR444
CAPACITOR ON OUTPUT
VDD1
FOR STABILITY
CREF
10µF1, 2
10µF1
(5V)
VDD2
100nF
(2.5V)
100nF
32 31 30 29 28 27 26 25
10nF
ADR2808
10µF
1 VDD1
2 VDD2
3 CAP1
VIO
CONTROL FOR
ENABLE
PINS
10kΩ3
10kΩ
4 REFIN
5 EN0
6 EN1
VDD2
(2.5V)
100nF
7 VDD2
CONVERSION4
CONTROL
CMOS (CNV+ ONLY)
OR
LVDS CNV+ AND CNV–
USING 100Ω
TERMINATION RESISTOR
8
9
100Ω
PADDLE
AD7626
GND 24
IN+ 23
IN– 22
VCM 21
IN+
IN– SEE THE DRIVING
THE AD7625 SECTION7
VCM
VDD1 20
VDD1 19
VDD2 18
100nF
FERRITE
BEAD6
VDD1
(5V)
100nF
VDD2
(2.5V)
10
11 12 13
100Ω
VIO
(2.5V)
14
15
16
17
5
100Ω
100Ω
DIGITAL INTERFACE SIGNALS
DIGITAL HOST
LVDS TRANSMIT AND RECEIVE
1 SEE THE LAYOUT, DECOUPLING, AND GROUNDING SECTION.
2
3
CREF IS USUALLY
USE PULL-UP OR
A 10µF CERAMIC CAPACITOR WITH LOW ESR AND ESL.
PULL-DOWN RESISTORS TO CONTROL EN0 AND EN1 DURING
POWER-UP.
EN0
AND
EN1
INPUTS
CAN
BE
FIXED IN HARDWARE OR CONTROLLED USING A DIGITAL HOST (EN0 = 0 AND EN1 = 0 PUTS THE ADC IN POWER-DOWN).
4 OPTION TO USE A CMOS (CNV+) OR LVDS (CNV±) INPUT TO CONTROL CONVERSIONS.
5 TO ENABLE SELF-CLOCKED MODE, TIE DCO+ TO GND.
6 CONNECT PIN 19 AND PIN 20 TO VDD1 SUPPLY; ISOLATE THE TRACE TO PIN 19 AND PIN 20 FROM THE TRACE TO PIN 1 USING A
FERRITE BEAD SIMILAR TO WURTH 74279266.
7 SEE THE DRIVING THE AD7626 SECTION FOR DETAILS ON AMPLIFIER CONFIGURATIONS.
8 SEE THE VOLTAGE REFERENCE OPTIONS SECTION FOR DETAILS.
Figure 31. Typical Application Diagram
Rev. A | Page 17 of
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