EVAL1002/AA View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'EVAL1002/AA' PDF : 19 Pages View PDF
TSA1002
Clock input
- Proper termination of all inputs and outputs is
The quality of your converter is very dependant on
your clock input accuracy, in terms of aperture
jitter; the use of low jitter crystal controlled
oscillator is recommended.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise
modulation at the output.
It is recommended to keep the circuit clocked, to
avoid random states, before applying the supply
voltages.
needed; with output termination resistors, the
amplifier load will be only resistive and the stability
N of the amplifier will be improved. All leads must be
wide and as short as possible especially for the
analog input in order to decrease parasitic
G capacitance and inductance.
I - To keep the capacitive loading as low as
S possible at digital outputs, short lead lengths of
routing are essential to minimize currents when
E the output changes. To minimize this output
capacitance, buffers or latches close to the output
D pins will relax this constraint.
Layout precautions
- Choose component sizes as small as possible
To use the ADC circuits in the best manner at high
frequencies, some precautions have to be taken
W for power supplies:
E ) - First of all, the implementation of 4 separate
t(s proper supplies and ground planes (analog,
N c digital, internal and external buffer ones) on the
u PCB is recommended for high speed circuit
d applications to provide low inductance and low
R ro resistance common return.
P The separation of the analog signal from the
O te digital part is essential to prevent noise from
le coupling onto the input signal.
F o - Power supply bypass capacitors must be placed
s as close as possible to the IC pins in order to
b improve high frequency bypassing and reduce
T O harmonic distortion.
(SMD).
EVAL1002 evaluation board
The characterization of the board has been made
with a fully ADC devoted test bench as shown on
Figure 11. The analog signal must be filtered to be
very pure.
The dataready signal is the acquisition clock of the
logic analyzer.
The ADC digital outputs are latched by the
74LCX573 octal buffers.
All characterization measurement has been made
with an input amplitude of +0.2dB for static
parameters and -0.5dB for dynamic parameters.
O t(s) - Figure 11 : Analog to Digital Converter characterization bench
N Produc HP8644
lete Sine Wave
ObsoGenerator
Data
Vin
ADC
evaluation
Logic
Analyzer
PC
board
Clk
Clk
HP8133
Pulse
Generator
Sine Wave
HP8644 Generator
17/20
Share Link: 
